[compiler-rt] [compiler-rt][RISCV] Implement __init_riscv_features_bit (PR #85790)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 26 04:17:52 PDT 2024
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85790
>From 628f3e88f82c699b8963394927d148afeb82398c Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Mon, 10 Jun 2024 21:24:05 -0700
Subject: [PATCH 01/13] [compiler-rt][RISCV] Implement
__riscv_feature_bits/__riscv_vendor_feature_bits/__init_riscv_features_bit
Base on https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74, this patch defines the __riscv_feature_bits and __riscv_vendor_feature_bits structures to store the enabled feature bits at runtime.
It also introduces the __init_riscv_features_bit function to update these structures based on the platform query mechanism.
Additionally, the groupid/bitmask definitions from https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74 are declared and used to update the __riscv_feature_bits and __riscv_vendor_feature_bits structures.
---
compiler-rt/lib/builtins/CMakeLists.txt | 1 +
compiler-rt/lib/builtins/riscv/ifunc_select.c | 527 ++++++++++++++++++
2 files changed, 528 insertions(+)
create mode 100644 compiler-rt/lib/builtins/riscv/ifunc_select.c
diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt
index c72eb337109cb..bcdc08b81d805 100644
--- a/compiler-rt/lib/builtins/CMakeLists.txt
+++ b/compiler-rt/lib/builtins/CMakeLists.txt
@@ -716,6 +716,7 @@ endif()
set(powerpc64le_SOURCES ${powerpc64_SOURCES})
set(riscv_SOURCES
+ riscv/ifunc_select.c
riscv/fp_mode.c
riscv/save.S
riscv/restore.S
diff --git a/compiler-rt/lib/builtins/riscv/ifunc_select.c b/compiler-rt/lib/builtins/riscv/ifunc_select.c
new file mode 100644
index 0000000000000..4ab01ace2d4b9
--- /dev/null
+++ b/compiler-rt/lib/builtins/riscv/ifunc_select.c
@@ -0,0 +1,527 @@
+//=== ifunc_select.c - Check environment hardware feature -*- C -*-===========//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
+ long arg4, long arg5) {
+ register long a7 __asm__("a7") = number;
+ register long a0 __asm__("a0") = arg1;
+ register long a1 __asm__("a1") = arg2;
+ register long a2 __asm__("a2") = arg3;
+ register long a3 __asm__("a3") = arg4;
+ register long a4 __asm__("a4") = arg5;
+ __asm__ __volatile__("ecall\n\t"
+ : "=r"(a0)
+ : "r"(a7), "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
+ : "memory");
+ return a0;
+}
+
+#define RISCV_HWPROBE_KEY_MVENDORID 0
+#define RISCV_HWPROBE_KEY_MARCHID 1
+#define RISCV_HWPROBE_KEY_MIMPID 2
+#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
+#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1ULL << 0)
+#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
+#define RISCV_HWPROBE_IMA_FD (1ULL << 0)
+#define RISCV_HWPROBE_IMA_C (1ULL << 1)
+#define RISCV_HWPROBE_IMA_V (1ULL << 2)
+#define RISCV_HWPROBE_EXT_ZBA (1ULL << 3)
+#define RISCV_HWPROBE_EXT_ZBB (1ULL << 4)
+#define RISCV_HWPROBE_EXT_ZBS (1ULL << 5)
+#define RISCV_HWPROBE_EXT_ZICBOZ (1ULL << 6)
+#define RISCV_HWPROBE_EXT_ZBC (1ULL << 7)
+#define RISCV_HWPROBE_EXT_ZBKB (1ULL << 8)
+#define RISCV_HWPROBE_EXT_ZBKC (1ULL << 9)
+#define RISCV_HWPROBE_EXT_ZBKX (1ULL << 10)
+#define RISCV_HWPROBE_EXT_ZKND (1ULL << 11)
+#define RISCV_HWPROBE_EXT_ZKNE (1ULL << 12)
+#define RISCV_HWPROBE_EXT_ZKNH (1ULL << 13)
+#define RISCV_HWPROBE_EXT_ZKSED (1ULL << 14)
+#define RISCV_HWPROBE_EXT_ZKSH (1ULL << 15)
+#define RISCV_HWPROBE_EXT_ZKT (1ULL << 16)
+#define RISCV_HWPROBE_EXT_ZVBB (1ULL << 17)
+#define RISCV_HWPROBE_EXT_ZVBC (1ULL << 18)
+#define RISCV_HWPROBE_EXT_ZVKB (1ULL << 19)
+#define RISCV_HWPROBE_EXT_ZVKG (1ULL << 20)
+#define RISCV_HWPROBE_EXT_ZVKNED (1ULL << 21)
+#define RISCV_HWPROBE_EXT_ZVKNHA (1ULL << 22)
+#define RISCV_HWPROBE_EXT_ZVKNHB (1ULL << 23)
+#define RISCV_HWPROBE_EXT_ZVKSED (1ULL << 24)
+#define RISCV_HWPROBE_EXT_ZVKSH (1ULL << 25)
+#define RISCV_HWPROBE_EXT_ZVKT (1ULL << 26)
+#define RISCV_HWPROBE_EXT_ZFH (1ULL << 27)
+#define RISCV_HWPROBE_EXT_ZFHMIN (1ULL << 28)
+#define RISCV_HWPROBE_EXT_ZIHINTNTL (1ULL << 29)
+#define RISCV_HWPROBE_EXT_ZVFH (1ULL << 30)
+#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
+#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
+#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
+#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
+#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
+#define RISCV_HWPROBE_KEY_CPUPERF_0 5
+#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
+#define RISCV_HWPROBE_MISALIGNED_EMULATED (1ULL << 0)
+#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
+#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
+#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
+#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
+#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
+/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
+
+/* Flags */
+#define RISCV_HWPROBE_WHICH_CPUS (1ULL << 0)
+
+struct riscv_hwprobe {
+ long long key;
+ unsigned long long value;
+};
+
+/* Size definition for CPU sets. */
+#define __CPU_SETSIZE 1024
+#define __NCPUBITS (8 * sizeof(unsigned long int))
+
+/* Data structure to describe CPU mask. */
+typedef struct {
+ unsigned long int __bits[__CPU_SETSIZE / __NCPUBITS];
+} cpu_set_t;
+
+#define SYS_riscv_hwprobe 258
+static long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, unsigned pair_count,
+ unsigned cpu_count, cpu_set_t *cpus,
+ unsigned int flags) {
+ return syscall_impl_5_args(SYS_riscv_hwprobe, (long)pairs, pair_count,
+ cpu_count, (long)cpus, flags);
+}
+
+static long initHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
+ return sys_riscv_hwprobe(Hwprobes, len, 0, (cpu_set_t *)((void *)0), 0);
+}
+
+struct {
+ unsigned length;
+ unsigned long long features[2];
+} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+struct {
+ unsigned vendorID;
+ unsigned length;
+ unsigned long long features[1];
+} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+// NOTE: Should sync-up with RISCVFeatures.td
+// TODO: Maybe generate a header from tablegen then include it.
+#define A_GROUPID 0
+#define A_BITMASK (1ULL << 22)
+#define C_GROUPID 0
+#define C_BITMASK (1ULL << 43)
+#define D_GROUPID 0
+#define D_BITMASK (1ULL << 34)
+#define E_GROUPID 0
+#define E_BITMASK (1ULL << 1)
+#define F_GROUPID 0
+#define F_BITMASK (1ULL << 33)
+#define H_GROUPID 1
+#define H_BITMASK (1ULL << 43)
+#define I_GROUPID 0
+#define I_BITMASK (1ULL << 0)
+#define M_GROUPID 0
+#define M_BITMASK (1ULL << 20)
+#define V_GROUPID 1
+#define V_BITMASK (1ULL << 22)
+#define ZA128RS_GROUPID 0
+#define ZA128RS_BITMASK (1ULL << 25)
+#define ZA64RS_GROUPID 0
+#define ZA64RS_BITMASK (1ULL << 24)
+#define ZAAMO_GROUPID 0
+#define ZAAMO_BITMASK (1ULL << 26)
+#define ZABHA_GROUPID 0
+#define ZABHA_BITMASK (1ULL << 27)
+#define ZACAS_GROUPID 0
+#define ZACAS_BITMASK (1ULL << 28)
+#define ZALASR_GROUPID 0
+#define ZALASR_BITMASK (1ULL << 29)
+#define ZALRSC_GROUPID 0
+#define ZALRSC_BITMASK (1ULL << 30)
+#define ZAMA16B_GROUPID 0
+#define ZAMA16B_BITMASK (1ULL << 31)
+#define ZAWRS_GROUPID 0
+#define ZAWRS_BITMASK (1ULL << 32)
+#define ZBA_GROUPID 0
+#define ZBA_BITMASK (1ULL << 52)
+#define ZBB_GROUPID 0
+#define ZBB_BITMASK (1ULL << 53)
+#define ZBC_GROUPID 0
+#define ZBC_BITMASK (1ULL << 54)
+#define ZBKB_GROUPID 0
+#define ZBKB_BITMASK (1ULL << 56)
+#define ZBKC_GROUPID 0
+#define ZBKC_BITMASK (1ULL << 58)
+#define ZBKX_GROUPID 0
+#define ZBKX_BITMASK (1ULL << 57)
+#define ZBS_GROUPID 0
+#define ZBS_BITMASK (1ULL << 55)
+#define ZCA_GROUPID 0
+#define ZCA_BITMASK (1ULL << 44)
+#define ZCB_GROUPID 0
+#define ZCB_BITMASK (1ULL << 45)
+#define ZCD_GROUPID 0
+#define ZCD_BITMASK (1ULL << 46)
+#define ZCE_GROUPID 0
+#define ZCE_BITMASK (1ULL << 50)
+#define ZCF_GROUPID 0
+#define ZCF_BITMASK (1ULL << 47)
+#define ZCMOP_GROUPID 0
+#define ZCMOP_BITMASK (1ULL << 51)
+#define ZCMP_GROUPID 0
+#define ZCMP_BITMASK (1ULL << 48)
+#define ZCMT_GROUPID 0
+#define ZCMT_BITMASK (1ULL << 49)
+#define ZDINX_GROUPID 0
+#define ZDINX_BITMASK (1ULL << 40)
+#define ZFA_GROUPID 0
+#define ZFA_BITMASK (1ULL << 38)
+#define ZFBFMIN_GROUPID 0
+#define ZFBFMIN_BITMASK (1ULL << 37)
+#define ZFH_GROUPID 0
+#define ZFH_BITMASK (1ULL << 36)
+#define ZFHMIN_GROUPID 0
+#define ZFHMIN_BITMASK (1ULL << 35)
+#define ZFINX_GROUPID 0
+#define ZFINX_BITMASK (1ULL << 39)
+#define ZHINX_GROUPID 0
+#define ZHINX_BITMASK (1ULL << 42)
+#define ZHINXMIN_GROUPID 0
+#define ZHINXMIN_BITMASK (1ULL << 41)
+#define ZIC64B_GROUPID 0
+#define ZIC64B_BITMASK (1ULL << 2)
+#define ZICBOM_GROUPID 0
+#define ZICBOM_BITMASK (1ULL << 3)
+#define ZICBOP_GROUPID 0
+#define ZICBOP_BITMASK (1ULL << 4)
+#define ZICBOZ_GROUPID 0
+#define ZICBOZ_BITMASK (1ULL << 5)
+#define ZICCAMOA_GROUPID 0
+#define ZICCAMOA_BITMASK (1ULL << 6)
+#define ZICCIF_GROUPID 0
+#define ZICCIF_BITMASK (1ULL << 7)
+#define ZICCLSM_GROUPID 0
+#define ZICCLSM_BITMASK (1ULL << 8)
+#define ZICCRSE_GROUPID 0
+#define ZICCRSE_BITMASK (1ULL << 9)
+#define ZICFILP_GROUPID 0
+#define ZICFILP_BITMASK (1ULL << 18)
+#define ZICFISS_GROUPID 0
+#define ZICFISS_BITMASK (1ULL << 19)
+#define ZICNTR_GROUPID 0
+#define ZICNTR_BITMASK (1ULL << 11)
+#define ZICOND_GROUPID 0
+#define ZICOND_BITMASK (1ULL << 12)
+#define ZICSR_GROUPID 0
+#define ZICSR_BITMASK (1ULL << 10)
+#define ZIFENCEI_GROUPID 0
+#define ZIFENCEI_BITMASK (1ULL << 13)
+#define ZIHINTNTL_GROUPID 0
+#define ZIHINTNTL_BITMASK (1ULL << 15)
+#define ZIHINTPAUSE_GROUPID 0
+#define ZIHINTPAUSE_BITMASK (1ULL << 14)
+#define ZIHPM_GROUPID 0
+#define ZIHPM_BITMASK (1ULL << 16)
+#define ZIMOP_GROUPID 0
+#define ZIMOP_BITMASK (1ULL << 17)
+#define ZK_GROUPID 1
+#define ZK_BITMASK (1ULL << 4)
+#define ZKN_GROUPID 1
+#define ZKN_BITMASK (1ULL << 1)
+#define ZKND_GROUPID 0
+#define ZKND_BITMASK (1ULL << 59)
+#define ZKNE_GROUPID 0
+#define ZKNE_BITMASK (1ULL << 60)
+#define ZKNH_GROUPID 0
+#define ZKNH_BITMASK (1ULL << 61)
+#define ZKR_GROUPID 1
+#define ZKR_BITMASK (1ULL << 0)
+#define ZKS_GROUPID 1
+#define ZKS_BITMASK (1ULL << 2)
+#define ZKSED_GROUPID 0
+#define ZKSED_BITMASK (1ULL << 62)
+#define ZKSH_GROUPID 0
+#define ZKSH_BITMASK (1ULL << 63)
+#define ZKT_GROUPID 1
+#define ZKT_BITMASK (1ULL << 3)
+#define ZMMUL_GROUPID 0
+#define ZMMUL_BITMASK (1ULL << 21)
+#define ZTSO_GROUPID 0
+#define ZTSO_BITMASK (1ULL << 23)
+#define ZVBB_GROUPID 1
+#define ZVBB_BITMASK (1ULL << 28)
+#define ZVBC_GROUPID 1
+#define ZVBC_BITMASK (1ULL << 29)
+#define ZVE32F_GROUPID 1
+#define ZVE32F_BITMASK (1ULL << 18)
+#define ZVE32X_GROUPID 1
+#define ZVE32X_BITMASK (1ULL << 17)
+#define ZVE64D_GROUPID 1
+#define ZVE64D_BITMASK (1ULL << 21)
+#define ZVE64F_GROUPID 1
+#define ZVE64F_BITMASK (1ULL << 20)
+#define ZVE64X_GROUPID 1
+#define ZVE64X_BITMASK (1ULL << 19)
+#define ZVFBFMIN_GROUPID 1
+#define ZVFBFMIN_BITMASK (1ULL << 23)
+#define ZVFBFWMA_GROUPID 1
+#define ZVFBFWMA_BITMASK (1ULL << 24)
+#define ZVFH_GROUPID 1
+#define ZVFH_BITMASK (1ULL << 26)
+#define ZVFHMIN_GROUPID 1
+#define ZVFHMIN_BITMASK (1ULL << 25)
+#define ZVKB_GROUPID 1
+#define ZVKB_BITMASK (1ULL << 27)
+#define ZVKG_GROUPID 1
+#define ZVKG_BITMASK (1ULL << 30)
+#define ZVKN_GROUPID 1
+#define ZVKN_BITMASK (1ULL << 37)
+#define ZVKNC_GROUPID 1
+#define ZVKNC_BITMASK (1ULL << 38)
+#define ZVKNED_GROUPID 1
+#define ZVKNED_BITMASK (1ULL << 31)
+#define ZVKNG_GROUPID 1
+#define ZVKNG_BITMASK (1ULL << 39)
+#define ZVKNHA_GROUPID 1
+#define ZVKNHA_BITMASK (1ULL << 32)
+#define ZVKNHB_GROUPID 1
+#define ZVKNHB_BITMASK (1ULL << 33)
+#define ZVKS_GROUPID 1
+#define ZVKS_BITMASK (1ULL << 40)
+#define ZVKSC_GROUPID 1
+#define ZVKSC_BITMASK (1ULL << 41)
+#define ZVKSED_GROUPID 1
+#define ZVKSED_BITMASK (1ULL << 34)
+#define ZVKSG_GROUPID 1
+#define ZVKSG_BITMASK (1ULL << 42)
+#define ZVKSH_GROUPID 1
+#define ZVKSH_BITMASK (1ULL << 35)
+#define ZVKT_GROUPID 1
+#define ZVKT_BITMASK (1ULL << 36)
+#define ZVL1024B_GROUPID 1
+#define ZVL1024B_BITMASK (1ULL << 10)
+#define ZVL128B_GROUPID 1
+#define ZVL128B_BITMASK (1ULL << 7)
+#define ZVL16384B_GROUPID 1
+#define ZVL16384B_BITMASK (1ULL << 14)
+#define ZVL2048B_GROUPID 1
+#define ZVL2048B_BITMASK (1ULL << 11)
+#define ZVL256B_GROUPID 1
+#define ZVL256B_BITMASK (1ULL << 8)
+#define ZVL32768B_GROUPID 1
+#define ZVL32768B_BITMASK (1ULL << 15)
+#define ZVL32B_GROUPID 1
+#define ZVL32B_BITMASK (1ULL << 5)
+#define ZVL4096B_GROUPID 1
+#define ZVL4096B_BITMASK (1ULL << 12)
+#define ZVL512B_GROUPID 1
+#define ZVL512B_BITMASK (1ULL << 9)
+#define ZVL64B_GROUPID 1
+#define ZVL64B_BITMASK (1ULL << 6)
+#define ZVL65536B_GROUPID 1
+#define ZVL65536B_BITMASK (1ULL << 16)
+#define ZVL8192B_GROUPID 1
+#define ZVL8192B_BITMASK (1ULL << 13)
+
+#define HWPROBE_LENGTH 3
+
+static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
+
+ // Init vendor extension
+ __riscv_vendor_feature_bits.length = 0;
+ __riscv_vendor_feature_bits.vendorID = Hwprobes[2].value;
+
+ // Init standard extension
+ // TODO: Maybe Extension implied generate from tablegen?
+ __riscv_feature_bits.length = 2;
+ // Check RISCV_HWPROBE_KEY_BASE_BEHAVIOR
+ unsigned long long BaseValue = Hwprobes[0].value;
+ if (BaseValue & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) {
+ __riscv_feature_bits.features[I_GROUPID] |= I_BITMASK;
+ __riscv_feature_bits.features[M_GROUPID] |= M_BITMASK;
+ __riscv_feature_bits.features[A_GROUPID] |= A_BITMASK;
+ }
+
+ // Check RISCV_HWPROBE_KEY_IMA_EXT_0
+ unsigned long long IMAEXT0Value = Hwprobes[1].value;
+ if (IMAEXT0Value & RISCV_HWPROBE_IMA_FD) {
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+ __riscv_feature_bits.features[D_GROUPID] |= D_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ }
+
+ if (IMAEXT0Value & RISCV_HWPROBE_IMA_C) {
+ __riscv_feature_bits.features[C_GROUPID] |= C_BITMASK;
+ }
+
+ if (IMAEXT0Value & RISCV_HWPROBE_IMA_V) {
+ __riscv_feature_bits.features[V_GROUPID] |= V_BITMASK;
+ __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
+ __riscv_feature_bits.features[ZVE64X_GROUPID] |= ZVE64X_BITMASK;
+ __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+ __riscv_feature_bits.features[ZVE64D_GROUPID] |= ZVE64D_BITMASK;
+ __riscv_feature_bits.features[D_GROUPID] |= D_BITMASK;
+ __riscv_feature_bits.features[ZVE32F_GROUPID] |= ZVE32F_BITMASK;
+ __riscv_feature_bits.features[ZVL128B_GROUPID] |= ZVL128B_BITMASK;
+ __riscv_feature_bits.features[ZVE64F_GROUPID] |= ZVE64F_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ __riscv_feature_bits.features[ZVL64B_GROUPID] |= ZVL64B_BITMASK;
+ }
+
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBA) {
+ __riscv_feature_bits.features[ZBA_GROUPID] |= ZBA_BITMASK;
+ }
+
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBB) {
+ __riscv_feature_bits.features[ZBB_GROUPID] |= ZBB_BITMASK;
+ }
+
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBS) {
+ __riscv_feature_bits.features[ZBS_GROUPID] |= ZBS_BITMASK;
+ }
+
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZICBOZ) {
+ __riscv_feature_bits.features[ZICBOZ_GROUPID] |= ZICBOZ_BITMASK;
+ }
+
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBC) {
+ __riscv_feature_bits.features[ZBC_GROUPID] |= ZBC_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBKB) {
+ __riscv_feature_bits.features[ZBKB_GROUPID] |= ZBKB_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBKC) {
+ __riscv_feature_bits.features[ZBKC_GROUPID] |= ZBKC_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBKX) {
+ __riscv_feature_bits.features[ZBKX_GROUPID] |= ZBKX_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKND) {
+ __riscv_feature_bits.features[ZKND_GROUPID] |= ZKND_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKNE) {
+ __riscv_feature_bits.features[ZKNE_GROUPID] |= ZKNE_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKNH) {
+ __riscv_feature_bits.features[ZKNH_GROUPID] |= ZKNH_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKSED) {
+ __riscv_feature_bits.features[ZKSED_GROUPID] |= ZKSED_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKSH) {
+ __riscv_feature_bits.features[ZKSH_GROUPID] |= ZKSH_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKT) {
+ __riscv_feature_bits.features[ZKT_GROUPID] |= ZKT_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVBB) {
+ __riscv_feature_bits.features[ZVBB_GROUPID] |= ZVBB_BITMASK;
+ __riscv_feature_bits.features[ZVKB_GROUPID] |= ZVKB_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVBC) {
+ __riscv_feature_bits.features[ZVBC_GROUPID] |= ZVBC_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKB) {
+ __riscv_feature_bits.features[ZVKB_GROUPID] |= ZVKB_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKG) {
+ __riscv_feature_bits.features[ZVKG_GROUPID] |= ZVKG_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKNED) {
+ __riscv_feature_bits.features[ZVKNED_GROUPID] |= ZVKNED_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKNHA) {
+ __riscv_feature_bits.features[ZVKNHA_GROUPID] |= ZVKNHA_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKNHB) {
+ __riscv_feature_bits.features[ZVKNHB_GROUPID] |= ZVKNHB_BITMASK;
+ __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
+ __riscv_feature_bits.features[ZVE64X_GROUPID] |= ZVE64X_BITMASK;
+ __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ __riscv_feature_bits.features[ZVL64B_GROUPID] |= ZVL64B_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKSED) {
+ __riscv_feature_bits.features[ZVKSED_GROUPID] |= ZVKSED_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKSH) {
+ __riscv_feature_bits.features[ZVKSH_GROUPID] |= ZVKSH_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKT) {
+ __riscv_feature_bits.features[ZVKT_GROUPID] |= ZVKT_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFH) {
+ __riscv_feature_bits.features[ZFH_GROUPID] |= ZFH_BITMASK;
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+ __riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFHMIN) {
+ __riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZIHINTNTL) {
+ __riscv_feature_bits.features[ZIHINTNTL_GROUPID] |= ZIHINTNTL_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVFH) {
+ __riscv_feature_bits.features[ZVFH_GROUPID] |= ZVFH_BITMASK;
+ __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
+ __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+ __riscv_feature_bits.features[ZVFHMIN_GROUPID] |= ZVFHMIN_BITMASK;
+ __riscv_feature_bits.features[ZVE32F_GROUPID] |= ZVE32F_BITMASK;
+ __riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVFHMIN) {
+ __riscv_feature_bits.features[ZVFHMIN_GROUPID] |= ZVFHMIN_BITMASK;
+ __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
+ __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+ __riscv_feature_bits.features[ZVE32F_GROUPID] |= ZVE32F_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFA) {
+ __riscv_feature_bits.features[ZFA_GROUPID] |= ZFA_BITMASK;
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZTSO) {
+ __riscv_feature_bits.features[ZTSO_GROUPID] |= ZTSO_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZACAS) {
+ __riscv_feature_bits.features[ZACAS_GROUPID] |= ZACAS_BITMASK;
+ }
+ if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZICOND) {
+ __riscv_feature_bits.features[ZICOND_GROUPID] |= ZICOND_BITMASK;
+ }
+}
+
+static int FeaturesBitCached = 0;
+
+void __init_riscv_features_bit() {
+
+ if (FeaturesBitCached)
+ return;
+
+ FeaturesBitCached = 1;
+
+ struct riscv_hwprobe Hwprobes[HWPROBE_LENGTH];
+ Hwprobes[0].key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR;
+ Hwprobes[1].key = RISCV_HWPROBE_KEY_IMA_EXT_0;
+ Hwprobes[2].key = RISCV_HWPROBE_KEY_MVENDORID;
+ initHwProbe(Hwprobes, HWPROBE_LENGTH);
+
+ initRISCVFeature(Hwprobes);
+}
>From 0979c3768f8d1ce9890b5db82142745d516c2629 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 12 Jun 2024 22:59:44 -0700
Subject: [PATCH 02/13] Update bitmask
---
compiler-rt/lib/builtins/riscv/ifunc_select.c | 264 ++++++------------
1 file changed, 90 insertions(+), 174 deletions(-)
diff --git a/compiler-rt/lib/builtins/riscv/ifunc_select.c b/compiler-rt/lib/builtins/riscv/ifunc_select.c
index 4ab01ace2d4b9..dbda1a9fa887a 100644
--- a/compiler-rt/lib/builtins/riscv/ifunc_select.c
+++ b/compiler-rt/lib/builtins/riscv/ifunc_select.c
@@ -116,221 +116,137 @@ struct {
// NOTE: Should sync-up with RISCVFeatures.td
// TODO: Maybe generate a header from tablegen then include it.
#define A_GROUPID 0
-#define A_BITMASK (1ULL << 22)
+#define A_BITMASK (1ULL << 0)
#define C_GROUPID 0
-#define C_BITMASK (1ULL << 43)
+#define C_BITMASK (1ULL << 2)
#define D_GROUPID 0
-#define D_BITMASK (1ULL << 34)
+#define D_BITMASK (1ULL << 3)
#define E_GROUPID 0
-#define E_BITMASK (1ULL << 1)
+#define E_BITMASK (1ULL << 4)
#define F_GROUPID 0
-#define F_BITMASK (1ULL << 33)
-#define H_GROUPID 1
-#define H_BITMASK (1ULL << 43)
+#define F_BITMASK (1ULL << 5)
#define I_GROUPID 0
-#define I_BITMASK (1ULL << 0)
+#define I_BITMASK (1ULL << 8)
#define M_GROUPID 0
-#define M_BITMASK (1ULL << 20)
-#define V_GROUPID 1
-#define V_BITMASK (1ULL << 22)
-#define ZA128RS_GROUPID 0
-#define ZA128RS_BITMASK (1ULL << 25)
-#define ZA64RS_GROUPID 0
-#define ZA64RS_BITMASK (1ULL << 24)
-#define ZAAMO_GROUPID 0
-#define ZAAMO_BITMASK (1ULL << 26)
-#define ZABHA_GROUPID 0
-#define ZABHA_BITMASK (1ULL << 27)
-#define ZACAS_GROUPID 0
-#define ZACAS_BITMASK (1ULL << 28)
-#define ZALASR_GROUPID 0
-#define ZALASR_BITMASK (1ULL << 29)
-#define ZALRSC_GROUPID 0
-#define ZALRSC_BITMASK (1ULL << 30)
-#define ZAMA16B_GROUPID 0
-#define ZAMA16B_BITMASK (1ULL << 31)
-#define ZAWRS_GROUPID 0
-#define ZAWRS_BITMASK (1ULL << 32)
-#define ZBA_GROUPID 0
-#define ZBA_BITMASK (1ULL << 52)
-#define ZBB_GROUPID 0
-#define ZBB_BITMASK (1ULL << 53)
-#define ZBC_GROUPID 0
-#define ZBC_BITMASK (1ULL << 54)
-#define ZBKB_GROUPID 0
-#define ZBKB_BITMASK (1ULL << 56)
-#define ZBKC_GROUPID 0
-#define ZBKC_BITMASK (1ULL << 58)
-#define ZBKX_GROUPID 0
-#define ZBKX_BITMASK (1ULL << 57)
-#define ZBS_GROUPID 0
-#define ZBS_BITMASK (1ULL << 55)
-#define ZCA_GROUPID 0
-#define ZCA_BITMASK (1ULL << 44)
-#define ZCB_GROUPID 0
-#define ZCB_BITMASK (1ULL << 45)
-#define ZCD_GROUPID 0
-#define ZCD_BITMASK (1ULL << 46)
-#define ZCE_GROUPID 0
-#define ZCE_BITMASK (1ULL << 50)
-#define ZCF_GROUPID 0
-#define ZCF_BITMASK (1ULL << 47)
-#define ZCMOP_GROUPID 0
-#define ZCMOP_BITMASK (1ULL << 51)
-#define ZCMP_GROUPID 0
-#define ZCMP_BITMASK (1ULL << 48)
-#define ZCMT_GROUPID 0
-#define ZCMT_BITMASK (1ULL << 49)
-#define ZDINX_GROUPID 0
-#define ZDINX_BITMASK (1ULL << 40)
-#define ZFA_GROUPID 0
-#define ZFA_BITMASK (1ULL << 38)
-#define ZFBFMIN_GROUPID 0
-#define ZFBFMIN_BITMASK (1ULL << 37)
-#define ZFH_GROUPID 0
-#define ZFH_BITMASK (1ULL << 36)
-#define ZFHMIN_GROUPID 0
-#define ZFHMIN_BITMASK (1ULL << 35)
-#define ZFINX_GROUPID 0
-#define ZFINX_BITMASK (1ULL << 39)
-#define ZHINX_GROUPID 0
-#define ZHINX_BITMASK (1ULL << 42)
-#define ZHINXMIN_GROUPID 0
-#define ZHINXMIN_BITMASK (1ULL << 41)
-#define ZIC64B_GROUPID 0
-#define ZIC64B_BITMASK (1ULL << 2)
-#define ZICBOM_GROUPID 0
-#define ZICBOM_BITMASK (1ULL << 3)
-#define ZICBOP_GROUPID 0
-#define ZICBOP_BITMASK (1ULL << 4)
-#define ZICBOZ_GROUPID 0
-#define ZICBOZ_BITMASK (1ULL << 5)
-#define ZICCAMOA_GROUPID 0
-#define ZICCAMOA_BITMASK (1ULL << 6)
-#define ZICCIF_GROUPID 0
-#define ZICCIF_BITMASK (1ULL << 7)
-#define ZICCLSM_GROUPID 0
-#define ZICCLSM_BITMASK (1ULL << 8)
-#define ZICCRSE_GROUPID 0
-#define ZICCRSE_BITMASK (1ULL << 9)
-#define ZICFILP_GROUPID 0
-#define ZICFILP_BITMASK (1ULL << 18)
-#define ZICFISS_GROUPID 0
-#define ZICFISS_BITMASK (1ULL << 19)
-#define ZICNTR_GROUPID 0
-#define ZICNTR_BITMASK (1ULL << 11)
-#define ZICOND_GROUPID 0
-#define ZICOND_BITMASK (1ULL << 12)
-#define ZICSR_GROUPID 0
-#define ZICSR_BITMASK (1ULL << 10)
-#define ZIFENCEI_GROUPID 0
-#define ZIFENCEI_BITMASK (1ULL << 13)
-#define ZIHINTNTL_GROUPID 0
-#define ZIHINTNTL_BITMASK (1ULL << 15)
-#define ZIHINTPAUSE_GROUPID 0
-#define ZIHINTPAUSE_BITMASK (1ULL << 14)
-#define ZIHPM_GROUPID 0
-#define ZIHPM_BITMASK (1ULL << 16)
-#define ZIMOP_GROUPID 0
-#define ZIMOP_BITMASK (1ULL << 17)
-#define ZK_GROUPID 1
-#define ZK_BITMASK (1ULL << 4)
-#define ZKN_GROUPID 1
-#define ZKN_BITMASK (1ULL << 1)
-#define ZKND_GROUPID 0
-#define ZKND_BITMASK (1ULL << 59)
-#define ZKNE_GROUPID 0
-#define ZKNE_BITMASK (1ULL << 60)
-#define ZKNH_GROUPID 0
-#define ZKNH_BITMASK (1ULL << 61)
+#define M_BITMASK (1ULL << 12)
+#define V_GROUPID 0
+#define V_BITMASK (1ULL << 21)
+#define ZACAS_GROUPID 1
+#define ZACAS_BITMASK (1ULL << 6)
+#define ZBA_GROUPID 1
+#define ZBA_BITMASK (1ULL << 55)
+#define ZBB_GROUPID 1
+#define ZBB_BITMASK (1ULL << 12)
+#define ZBC_GROUPID 1
+#define ZBC_BITMASK (1ULL << 13)
+#define ZBKB_GROUPID 1
+#define ZBKB_BITMASK (1ULL << 15)
+#define ZBKC_GROUPID 1
+#define ZBKC_BITMASK (1ULL << 17)
+#define ZBKX_GROUPID 1
+#define ZBKX_BITMASK (1ULL << 16)
+#define ZBS_GROUPID 1
+#define ZBS_BITMASK (1ULL << 14)
+#define ZCA_GROUPID 1
+#define ZCA_BITMASK (1ULL << 11)
+#define ZFA_GROUPID 1
+#define ZFA_BITMASK (1ULL << 9)
+#define ZFH_GROUPID 1
+#define ZFH_BITMASK (1ULL << 8)
+#define ZFHMIN_GROUPID 1
+#define ZFHMIN_BITMASK (1ULL << 7)
+#define ZHINX_GROUPID 1
+#define ZHINX_BITMASK (1ULL << 10)
+#define ZICBOZ_GROUPID 1
+#define ZICBOZ_BITMASK (1ULL << 0)
+#define ZICOND_GROUPID 1
+#define ZICOND_BITMASK (1ULL << 2)
+#define ZICSR_GROUPID 1
+#define ZICSR_BITMASK (1ULL << 1)
+#define ZIHINTNTL_GROUPID 1
+#define ZIHINTNTL_BITMASK (1ULL << 3)
+#define ZKND_GROUPID 1
+#define ZKND_BITMASK (1ULL << 18)
+#define ZKNE_GROUPID 1
+#define ZKNE_BITMASK (1ULL << 19)
+#define ZKNH_GROUPID 1
+#define ZKNH_BITMASK (1ULL << 20)
#define ZKR_GROUPID 1
-#define ZKR_BITMASK (1ULL << 0)
-#define ZKS_GROUPID 1
-#define ZKS_BITMASK (1ULL << 2)
-#define ZKSED_GROUPID 0
-#define ZKSED_BITMASK (1ULL << 62)
-#define ZKSH_GROUPID 0
-#define ZKSH_BITMASK (1ULL << 63)
+#define ZKR_BITMASK (1ULL << 23)
+#define ZKSED_GROUPID 1
+#define ZKSED_BITMASK (1ULL << 21)
+#define ZKSH_GROUPID 1
+#define ZKSH_BITMASK (1ULL << 22)
#define ZKT_GROUPID 1
-#define ZKT_BITMASK (1ULL << 3)
-#define ZMMUL_GROUPID 0
-#define ZMMUL_BITMASK (1ULL << 21)
-#define ZTSO_GROUPID 0
-#define ZTSO_BITMASK (1ULL << 23)
+#define ZKT_BITMASK (1ULL << 24)
+#define ZTSO_GROUPID 1
+#define ZTSO_BITMASK (1ULL << 5)
#define ZVBB_GROUPID 1
-#define ZVBB_BITMASK (1ULL << 28)
+#define ZVBB_BITMASK (1ULL << 46)
#define ZVBC_GROUPID 1
-#define ZVBC_BITMASK (1ULL << 29)
+#define ZVBC_BITMASK (1ULL << 47)
#define ZVE32F_GROUPID 1
-#define ZVE32F_BITMASK (1ULL << 18)
+#define ZVE32F_BITMASK (1ULL << 38)
#define ZVE32X_GROUPID 1
-#define ZVE32X_BITMASK (1ULL << 17)
+#define ZVE32X_BITMASK (1ULL << 37)
#define ZVE64D_GROUPID 1
-#define ZVE64D_BITMASK (1ULL << 21)
+#define ZVE64D_BITMASK (1ULL << 41)
#define ZVE64F_GROUPID 1
-#define ZVE64F_BITMASK (1ULL << 20)
+#define ZVE64F_BITMASK (1ULL << 40)
#define ZVE64X_GROUPID 1
-#define ZVE64X_BITMASK (1ULL << 19)
-#define ZVFBFMIN_GROUPID 1
-#define ZVFBFMIN_BITMASK (1ULL << 23)
-#define ZVFBFWMA_GROUPID 1
-#define ZVFBFWMA_BITMASK (1ULL << 24)
+#define ZVE64X_BITMASK (1ULL << 39)
#define ZVFH_GROUPID 1
-#define ZVFH_BITMASK (1ULL << 26)
+#define ZVFH_BITMASK (1ULL << 44)
#define ZVFHMIN_GROUPID 1
-#define ZVFHMIN_BITMASK (1ULL << 25)
+#define ZVFHMIN_BITMASK (1ULL << 43)
#define ZVKB_GROUPID 1
-#define ZVKB_BITMASK (1ULL << 27)
+#define ZVKB_BITMASK (1ULL << 45)
#define ZVKG_GROUPID 1
-#define ZVKG_BITMASK (1ULL << 30)
+#define ZVKG_BITMASK (1ULL << 48)
#define ZVKN_GROUPID 1
-#define ZVKN_BITMASK (1ULL << 37)
-#define ZVKNC_GROUPID 1
-#define ZVKNC_BITMASK (1ULL << 38)
+#define ZVKN_BITMASK (1ULL << 56)
#define ZVKNED_GROUPID 1
-#define ZVKNED_BITMASK (1ULL << 31)
+#define ZVKNED_BITMASK (1ULL << 49)
#define ZVKNG_GROUPID 1
-#define ZVKNG_BITMASK (1ULL << 39)
+#define ZVKNG_BITMASK (1ULL << 57)
#define ZVKNHA_GROUPID 1
-#define ZVKNHA_BITMASK (1ULL << 32)
+#define ZVKNHA_BITMASK (1ULL << 50)
#define ZVKNHB_GROUPID 1
-#define ZVKNHB_BITMASK (1ULL << 33)
+#define ZVKNHB_BITMASK (1ULL << 51)
#define ZVKS_GROUPID 1
-#define ZVKS_BITMASK (1ULL << 40)
-#define ZVKSC_GROUPID 1
-#define ZVKSC_BITMASK (1ULL << 41)
+#define ZVKS_BITMASK (1ULL << 58)
#define ZVKSED_GROUPID 1
-#define ZVKSED_BITMASK (1ULL << 34)
+#define ZVKSED_BITMASK (1ULL << 52)
#define ZVKSG_GROUPID 1
-#define ZVKSG_BITMASK (1ULL << 42)
+#define ZVKSG_BITMASK (1ULL << 59)
#define ZVKSH_GROUPID 1
-#define ZVKSH_BITMASK (1ULL << 35)
+#define ZVKSH_BITMASK (1ULL << 53)
#define ZVKT_GROUPID 1
-#define ZVKT_BITMASK (1ULL << 36)
+#define ZVKT_BITMASK (1ULL << 54)
#define ZVL1024B_GROUPID 1
-#define ZVL1024B_BITMASK (1ULL << 10)
+#define ZVL1024B_BITMASK (1ULL << 30)
#define ZVL128B_GROUPID 1
-#define ZVL128B_BITMASK (1ULL << 7)
+#define ZVL128B_BITMASK (1ULL << 27)
#define ZVL16384B_GROUPID 1
-#define ZVL16384B_BITMASK (1ULL << 14)
+#define ZVL16384B_BITMASK (1ULL << 34)
#define ZVL2048B_GROUPID 1
-#define ZVL2048B_BITMASK (1ULL << 11)
+#define ZVL2048B_BITMASK (1ULL << 31)
#define ZVL256B_GROUPID 1
-#define ZVL256B_BITMASK (1ULL << 8)
+#define ZVL256B_BITMASK (1ULL << 28)
#define ZVL32768B_GROUPID 1
-#define ZVL32768B_BITMASK (1ULL << 15)
+#define ZVL32768B_BITMASK (1ULL << 35)
#define ZVL32B_GROUPID 1
-#define ZVL32B_BITMASK (1ULL << 5)
+#define ZVL32B_BITMASK (1ULL << 25)
#define ZVL4096B_GROUPID 1
-#define ZVL4096B_BITMASK (1ULL << 12)
+#define ZVL4096B_BITMASK (1ULL << 32)
#define ZVL512B_GROUPID 1
-#define ZVL512B_BITMASK (1ULL << 9)
+#define ZVL512B_BITMASK (1ULL << 29)
#define ZVL64B_GROUPID 1
-#define ZVL64B_BITMASK (1ULL << 6)
+#define ZVL64B_BITMASK (1ULL << 26)
#define ZVL65536B_GROUPID 1
-#define ZVL65536B_BITMASK (1ULL << 16)
+#define ZVL65536B_BITMASK (1ULL << 36)
#define ZVL8192B_GROUPID 1
-#define ZVL8192B_BITMASK (1ULL << 13)
+#define ZVL8192B_BITMASK (1ULL << 33)
#define HWPROBE_LENGTH 3
>From e0a712c32f47a42b8a9f55886ee6f9aa80c38591 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Thu, 13 Jun 2024 01:56:42 -0700
Subject: [PATCH 03/13] Rename ifunc_select with feature_bits
---
compiler-rt/lib/builtins/CMakeLists.txt | 2 +-
.../lib/builtins/riscv/{ifunc_select.c => feature_bits.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename compiler-rt/lib/builtins/riscv/{ifunc_select.c => feature_bits.c} (100%)
diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt
index bcdc08b81d805..263ec85b43637 100644
--- a/compiler-rt/lib/builtins/CMakeLists.txt
+++ b/compiler-rt/lib/builtins/CMakeLists.txt
@@ -716,7 +716,7 @@ endif()
set(powerpc64le_SOURCES ${powerpc64_SOURCES})
set(riscv_SOURCES
- riscv/ifunc_select.c
+ riscv/feature_bits.c
riscv/fp_mode.c
riscv/save.S
riscv/restore.S
diff --git a/compiler-rt/lib/builtins/riscv/ifunc_select.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
similarity index 100%
rename from compiler-rt/lib/builtins/riscv/ifunc_select.c
rename to compiler-rt/lib/builtins/riscv/feature_bits.c
>From bbc63d6b9e681ea353daddb5f952e64f4b4d8c0b Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Fri, 14 Jun 2024 03:41:05 -0700
Subject: [PATCH 04/13] Update comment
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index dbda1a9fa887a..cbe8fc860ee0e 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -1,4 +1,4 @@
-//=== ifunc_select.c - Check environment hardware feature -*- C -*-===========//
+//=== feature_bits.c - Update RISC-V Feature Bits Structure -*- C -*-=========//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
>From e43b30cdacfabfe88ce14fd64b1999a2cf5247a9 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Fri, 14 Jun 2024 04:22:40 -0700
Subject: [PATCH 05/13] Extract Implied extension into new help function
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 123 ++++++++++++------
1 file changed, 82 insertions(+), 41 deletions(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index cbe8fc860ee0e..880ea88959e80 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -102,15 +102,17 @@ static long initHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
return sys_riscv_hwprobe(Hwprobes, len, 0, (cpu_set_t *)((void *)0), 0);
}
+#define RISCV_FEATURE_BITS_LENGTH 2
struct {
unsigned length;
- unsigned long long features[2];
+ unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
+#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
struct {
unsigned vendorID;
unsigned length;
- unsigned long long features[1];
+ unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
// NOTE: Should sync-up with RISCVFeatures.td
@@ -155,8 +157,6 @@ struct {
#define ZFH_BITMASK (1ULL << 8)
#define ZFHMIN_GROUPID 1
#define ZFHMIN_BITMASK (1ULL << 7)
-#define ZHINX_GROUPID 1
-#define ZHINX_BITMASK (1ULL << 10)
#define ZICBOZ_GROUPID 1
#define ZICBOZ_BITMASK (1ULL << 0)
#define ZICOND_GROUPID 1
@@ -272,7 +272,6 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
if (IMAEXT0Value & RISCV_HWPROBE_IMA_FD) {
__riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
__riscv_feature_bits.features[D_GROUPID] |= D_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_IMA_C) {
@@ -281,17 +280,6 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
if (IMAEXT0Value & RISCV_HWPROBE_IMA_V) {
__riscv_feature_bits.features[V_GROUPID] |= V_BITMASK;
- __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
- __riscv_feature_bits.features[ZVE64X_GROUPID] |= ZVE64X_BITMASK;
- __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
- __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
- __riscv_feature_bits.features[ZVE64D_GROUPID] |= ZVE64D_BITMASK;
- __riscv_feature_bits.features[D_GROUPID] |= D_BITMASK;
- __riscv_feature_bits.features[ZVE32F_GROUPID] |= ZVE32F_BITMASK;
- __riscv_feature_bits.features[ZVL128B_GROUPID] |= ZVL128B_BITMASK;
- __riscv_feature_bits.features[ZVE64F_GROUPID] |= ZVE64F_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
- __riscv_feature_bits.features[ZVL64B_GROUPID] |= ZVL64B_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBA) {
@@ -342,7 +330,6 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVBB) {
__riscv_feature_bits.features[ZVBB_GROUPID] |= ZVBB_BITMASK;
- __riscv_feature_bits.features[ZVKB_GROUPID] |= ZVKB_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVBC) {
__riscv_feature_bits.features[ZVBC_GROUPID] |= ZVBC_BITMASK;
@@ -361,11 +348,6 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKNHB) {
__riscv_feature_bits.features[ZVKNHB_GROUPID] |= ZVKNHB_BITMASK;
- __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
- __riscv_feature_bits.features[ZVE64X_GROUPID] |= ZVE64X_BITMASK;
- __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
- __riscv_feature_bits.features[ZVL64B_GROUPID] |= ZVL64B_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKSED) {
__riscv_feature_bits.features[ZVKSED_GROUPID] |= ZVKSED_BITMASK;
@@ -378,40 +360,21 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFH) {
__riscv_feature_bits.features[ZFH_GROUPID] |= ZFH_BITMASK;
- __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
- __riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFHMIN) {
__riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
- __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZIHINTNTL) {
__riscv_feature_bits.features[ZIHINTNTL_GROUPID] |= ZIHINTNTL_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVFH) {
__riscv_feature_bits.features[ZVFH_GROUPID] |= ZVFH_BITMASK;
- __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
- __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
- __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
- __riscv_feature_bits.features[ZVFHMIN_GROUPID] |= ZVFHMIN_BITMASK;
- __riscv_feature_bits.features[ZVE32F_GROUPID] |= ZVE32F_BITMASK;
- __riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVFHMIN) {
__riscv_feature_bits.features[ZVFHMIN_GROUPID] |= ZVFHMIN_BITMASK;
- __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
- __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
- __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
- __riscv_feature_bits.features[ZVE32F_GROUPID] |= ZVE32F_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFA) {
__riscv_feature_bits.features[ZFA_GROUPID] |= ZFA_BITMASK;
- __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
- __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
}
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZTSO) {
__riscv_feature_bits.features[ZTSO_GROUPID] |= ZTSO_BITMASK;
@@ -424,6 +387,83 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
}
}
+static unsigned updateImpliedFeaturesImpl() {
+
+ unsigned long long OriFeaturesBits[RISCV_FEATURE_BITS_LENGTH];
+ for (unsigned i = 0; i < __riscv_feature_bits.length; i++)
+ OriFeaturesBits[i] = __riscv_feature_bits.features[i];
+
+ if (__riscv_feature_bits.features[D_GROUPID] & D_BITMASK)
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+
+ if (__riscv_feature_bits.features[F_GROUPID] & F_BITMASK)
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+
+ if (__riscv_feature_bits.features[V_GROUPID] & V_BITMASK)
+ __riscv_feature_bits.features[ZVL128B_GROUPID] |= ZVL128B_BITMASK;
+
+ if (__riscv_feature_bits.features[V_GROUPID] & V_BITMASK)
+ __riscv_feature_bits.features[ZVE64D_GROUPID] |= ZVE64D_BITMASK;
+
+ if (__riscv_feature_bits.features[ZFA_GROUPID] & ZFA_BITMASK)
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+
+ if (__riscv_feature_bits.features[ZFH_GROUPID] & ZFH_BITMASK)
+ __riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
+
+ if (__riscv_feature_bits.features[ZFHMIN_GROUPID] & ZFHMIN_BITMASK)
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVBB_GROUPID] & ZVBB_BITMASK)
+ __riscv_feature_bits.features[ZVKB_GROUPID] |= ZVKB_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE32F_GROUPID] & ZVE32F_BITMASK)
+ __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE32F_GROUPID] & ZVE32F_BITMASK)
+ __riscv_feature_bits.features[F_GROUPID] |= F_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE32X_GROUPID] & ZVE32X_BITMASK)
+ __riscv_feature_bits.features[ZICSR_GROUPID] |= ZICSR_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE32X_GROUPID] & ZVE32X_BITMASK)
+ __riscv_feature_bits.features[ZVL32B_GROUPID] |= ZVL32B_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE64D_GROUPID] & ZVE64D_BITMASK)
+ __riscv_feature_bits.features[ZVE64F_GROUPID] |= ZVE64F_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE64D_GROUPID] & ZVE64D_BITMASK)
+ __riscv_feature_bits.features[D_GROUPID] |= D_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE64F_GROUPID] & ZVE64F_BITMASK)
+ __riscv_feature_bits.features[ZVE32F_GROUPID] |= ZVE32F_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE64F_GROUPID] & ZVE64F_BITMASK)
+ __riscv_feature_bits.features[ZVE64X_GROUPID] |= ZVE64X_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE64X_GROUPID] & ZVE64X_BITMASK)
+ __riscv_feature_bits.features[ZVE32X_GROUPID] |= ZVE32X_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVE64X_GROUPID] & ZVE64X_BITMASK)
+ __riscv_feature_bits.features[ZVL64B_GROUPID] |= ZVL64B_BITMASK;
+
+ if (__riscv_feature_bits.features[ZVFH_GROUPID] & ZVFH_BITMASK)
+ __riscv_feature_bits.features[ZVFHMIN_GROUPID] |= ZVFHMIN_BITMASK;
+
+ for (unsigned i = 0; i < __riscv_feature_bits.length; i++)
+ if (OriFeaturesBits[i] != __riscv_feature_bits.features[i])
+ return 1;
+
+ return 0;
+}
+
+void updateImpliedFeatures() {
+ unsigned Changed = 1;
+
+ while (Changed)
+ Changed = updateImpliedFeaturesImpl();
+}
+
static int FeaturesBitCached = 0;
void __init_riscv_features_bit() {
@@ -440,4 +480,5 @@ void __init_riscv_features_bit() {
initHwProbe(Hwprobes, HWPROBE_LENGTH);
initRISCVFeature(Hwprobes);
+ updateImpliedFeatures();
}
>From 06309cc7858ee612b0e16013605aab4c04192648 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 02:33:44 -0700
Subject: [PATCH 06/13] Rename syscall number name
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index 880ea88959e80..d87c98706f1b1 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -90,11 +90,11 @@ typedef struct {
unsigned long int __bits[__CPU_SETSIZE / __NCPUBITS];
} cpu_set_t;
-#define SYS_riscv_hwprobe 258
+#define __NR_riscv_hwprobe 258
static long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, unsigned pair_count,
unsigned cpu_count, cpu_set_t *cpus,
unsigned int flags) {
- return syscall_impl_5_args(SYS_riscv_hwprobe, (long)pairs, pair_count,
+ return syscall_impl_5_args(__NR_riscv_hwprobe, (long)pairs, pair_count,
cpu_count, (long)cpus, flags);
}
>From f4913051d584fc467cb98470274514202fc77ccb Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 02:34:12 -0700
Subject: [PATCH 07/13] Add static
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index d87c98706f1b1..7aa96ef95280b 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -457,7 +457,7 @@ static unsigned updateImpliedFeaturesImpl() {
return 0;
}
-void updateImpliedFeatures() {
+static void updateImpliedFeatures() {
unsigned Changed = 1;
while (Changed)
>From f7231df2b4b81f94beffb26a77d35b96d69852cc Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 02:34:59 -0700
Subject: [PATCH 08/13] Improve format
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index 7aa96ef95280b..d9167ef7c0698 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -301,87 +301,115 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBC) {
__riscv_feature_bits.features[ZBC_GROUPID] |= ZBC_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBKB) {
__riscv_feature_bits.features[ZBKB_GROUPID] |= ZBKB_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBKC) {
__riscv_feature_bits.features[ZBKC_GROUPID] |= ZBKC_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZBKX) {
__riscv_feature_bits.features[ZBKX_GROUPID] |= ZBKX_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKND) {
__riscv_feature_bits.features[ZKND_GROUPID] |= ZKND_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKNE) {
__riscv_feature_bits.features[ZKNE_GROUPID] |= ZKNE_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKNH) {
__riscv_feature_bits.features[ZKNH_GROUPID] |= ZKNH_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKSED) {
__riscv_feature_bits.features[ZKSED_GROUPID] |= ZKSED_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKSH) {
__riscv_feature_bits.features[ZKSH_GROUPID] |= ZKSH_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZKT) {
__riscv_feature_bits.features[ZKT_GROUPID] |= ZKT_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVBB) {
__riscv_feature_bits.features[ZVBB_GROUPID] |= ZVBB_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVBC) {
__riscv_feature_bits.features[ZVBC_GROUPID] |= ZVBC_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKB) {
__riscv_feature_bits.features[ZVKB_GROUPID] |= ZVKB_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKG) {
__riscv_feature_bits.features[ZVKG_GROUPID] |= ZVKG_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKNED) {
__riscv_feature_bits.features[ZVKNED_GROUPID] |= ZVKNED_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKNHA) {
__riscv_feature_bits.features[ZVKNHA_GROUPID] |= ZVKNHA_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKNHB) {
__riscv_feature_bits.features[ZVKNHB_GROUPID] |= ZVKNHB_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKSED) {
__riscv_feature_bits.features[ZVKSED_GROUPID] |= ZVKSED_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKSH) {
__riscv_feature_bits.features[ZVKSH_GROUPID] |= ZVKSH_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVKT) {
__riscv_feature_bits.features[ZVKT_GROUPID] |= ZVKT_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFH) {
__riscv_feature_bits.features[ZFH_GROUPID] |= ZFH_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFHMIN) {
__riscv_feature_bits.features[ZFHMIN_GROUPID] |= ZFHMIN_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZIHINTNTL) {
__riscv_feature_bits.features[ZIHINTNTL_GROUPID] |= ZIHINTNTL_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVFH) {
__riscv_feature_bits.features[ZVFH_GROUPID] |= ZVFH_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZVFHMIN) {
__riscv_feature_bits.features[ZVFHMIN_GROUPID] |= ZVFHMIN_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZFA) {
__riscv_feature_bits.features[ZFA_GROUPID] |= ZFA_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZTSO) {
__riscv_feature_bits.features[ZTSO_GROUPID] |= ZTSO_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZACAS) {
__riscv_feature_bits.features[ZACAS_GROUPID] |= ZACAS_BITMASK;
}
+
if (IMAEXT0Value & RISCV_HWPROBE_EXT_ZICOND) {
__riscv_feature_bits.features[ZICOND_GROUPID] |= ZICOND_BITMASK;
}
>From c00722c63115b456896c96402f6bd76fb30d9cef Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 02:41:24 -0700
Subject: [PATCH 09/13] Guard by linux marco
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index d9167ef7c0698..beb2c8ccb45d4 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -6,6 +6,8 @@
//
//===----------------------------------------------------------------------===//
+#if defined(__linux__)
+
static long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
long arg4, long arg5) {
register long a7 __asm__("a7") = number;
@@ -492,6 +494,8 @@ static void updateImpliedFeatures() {
Changed = updateImpliedFeaturesImpl();
}
+#endif // defined(__linux__)
+
static int FeaturesBitCached = 0;
void __init_riscv_features_bit() {
@@ -501,6 +505,7 @@ void __init_riscv_features_bit() {
FeaturesBitCached = 1;
+#if defined(__linux__)
struct riscv_hwprobe Hwprobes[HWPROBE_LENGTH];
Hwprobes[0].key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR;
Hwprobes[1].key = RISCV_HWPROBE_KEY_IMA_EXT_0;
@@ -509,4 +514,5 @@ void __init_riscv_features_bit() {
initRISCVFeature(Hwprobes);
updateImpliedFeatures();
+#endif // defined(__linux__)
}
>From a378f83881c010e080830c23173636bf0752a0e2 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 02:49:37 -0700
Subject: [PATCH 10/13] inline sys_riscv_hwprobe
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index beb2c8ccb45d4..c8ca7f638b74c 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -93,15 +93,9 @@ typedef struct {
} cpu_set_t;
#define __NR_riscv_hwprobe 258
-static long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, unsigned pair_count,
- unsigned cpu_count, cpu_set_t *cpus,
- unsigned int flags) {
- return syscall_impl_5_args(__NR_riscv_hwprobe, (long)pairs, pair_count,
- cpu_count, (long)cpus, flags);
-}
-
static long initHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
- return sys_riscv_hwprobe(Hwprobes, len, 0, (cpu_set_t *)((void *)0), 0);
+ return syscall_impl_5_args(__NR_riscv_hwprobe, (long)Hwprobes, len, 0,
+ (long)(cpu_set_t *)((void *)0), 0);
}
#define RISCV_FEATURE_BITS_LENGTH 2
>From 3e8d57f947fe6ed70fbd80e0d7e855edc505fb36 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 02:51:40 -0700
Subject: [PATCH 11/13] Refine struct riscv_hwprobe Hwprobes init
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index c8ca7f638b74c..5216207388894 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -500,11 +500,12 @@ void __init_riscv_features_bit() {
FeaturesBitCached = 1;
#if defined(__linux__)
- struct riscv_hwprobe Hwprobes[HWPROBE_LENGTH];
- Hwprobes[0].key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR;
- Hwprobes[1].key = RISCV_HWPROBE_KEY_IMA_EXT_0;
- Hwprobes[2].key = RISCV_HWPROBE_KEY_MVENDORID;
- initHwProbe(Hwprobes, HWPROBE_LENGTH);
+ struct riscv_hwprobe Hwprobes[] = {
+ {RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0},
+ {RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
+ {RISCV_HWPROBE_KEY_MVENDORID, 0},
+ };
+ initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0]));
initRISCVFeature(Hwprobes);
updateImpliedFeatures();
>From 2589b56df558a6bafc97e8eb7d77c98dd1c29fa0 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 02:53:52 -0700
Subject: [PATCH 12/13] Check initHwProbe return value
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index 5216207388894..8c2d421233ac1 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -505,7 +505,8 @@ void __init_riscv_features_bit() {
{RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
{RISCV_HWPROBE_KEY_MVENDORID, 0},
};
- initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0]));
+ if (initHwProbe(Hwprobes, sizeof(Hwprobes) / sizeof(Hwprobes[0])))
+ return ;
initRISCVFeature(Hwprobes);
updateImpliedFeatures();
>From c63a0f67a913e868d692c0596e7687b2b5809b15 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 26 Jun 2024 03:17:23 -0700
Subject: [PATCH 13/13] Align with RISCVFeatures.td
---
compiler-rt/lib/builtins/riscv/feature_bits.c | 192 ++++++++----------
1 file changed, 89 insertions(+), 103 deletions(-)
diff --git a/compiler-rt/lib/builtins/riscv/feature_bits.c b/compiler-rt/lib/builtins/riscv/feature_bits.c
index 8c2d421233ac1..21a7f0c892a5e 100644
--- a/compiler-rt/lib/builtins/riscv/feature_bits.c
+++ b/compiler-rt/lib/builtins/riscv/feature_bits.c
@@ -119,8 +119,6 @@ struct {
#define C_BITMASK (1ULL << 2)
#define D_GROUPID 0
#define D_BITMASK (1ULL << 3)
-#define E_GROUPID 0
-#define E_BITMASK (1ULL << 4)
#define F_GROUPID 0
#define F_BITMASK (1ULL << 5)
#define I_GROUPID 0
@@ -129,120 +127,108 @@ struct {
#define M_BITMASK (1ULL << 12)
#define V_GROUPID 0
#define V_BITMASK (1ULL << 21)
-#define ZACAS_GROUPID 1
-#define ZACAS_BITMASK (1ULL << 6)
-#define ZBA_GROUPID 1
-#define ZBA_BITMASK (1ULL << 55)
-#define ZBB_GROUPID 1
-#define ZBB_BITMASK (1ULL << 12)
-#define ZBC_GROUPID 1
-#define ZBC_BITMASK (1ULL << 13)
-#define ZBKB_GROUPID 1
-#define ZBKB_BITMASK (1ULL << 15)
-#define ZBKC_GROUPID 1
-#define ZBKC_BITMASK (1ULL << 17)
-#define ZBKX_GROUPID 1
-#define ZBKX_BITMASK (1ULL << 16)
-#define ZBS_GROUPID 1
-#define ZBS_BITMASK (1ULL << 14)
-#define ZCA_GROUPID 1
-#define ZCA_BITMASK (1ULL << 11)
-#define ZFA_GROUPID 1
-#define ZFA_BITMASK (1ULL << 9)
-#define ZFH_GROUPID 1
-#define ZFH_BITMASK (1ULL << 8)
-#define ZFHMIN_GROUPID 1
-#define ZFHMIN_BITMASK (1ULL << 7)
-#define ZICBOZ_GROUPID 1
-#define ZICBOZ_BITMASK (1ULL << 0)
-#define ZICOND_GROUPID 1
-#define ZICOND_BITMASK (1ULL << 2)
-#define ZICSR_GROUPID 1
-#define ZICSR_BITMASK (1ULL << 1)
-#define ZIHINTNTL_GROUPID 1
-#define ZIHINTNTL_BITMASK (1ULL << 3)
-#define ZKND_GROUPID 1
-#define ZKND_BITMASK (1ULL << 18)
-#define ZKNE_GROUPID 1
-#define ZKNE_BITMASK (1ULL << 19)
-#define ZKNH_GROUPID 1
-#define ZKNH_BITMASK (1ULL << 20)
-#define ZKR_GROUPID 1
-#define ZKR_BITMASK (1ULL << 23)
-#define ZKSED_GROUPID 1
-#define ZKSED_BITMASK (1ULL << 21)
-#define ZKSH_GROUPID 1
-#define ZKSH_BITMASK (1ULL << 22)
-#define ZKT_GROUPID 1
-#define ZKT_BITMASK (1ULL << 24)
-#define ZTSO_GROUPID 1
-#define ZTSO_BITMASK (1ULL << 5)
+#define ZACAS_GROUPID 0
+#define ZACAS_BITMASK (1ULL << 31)
+#define ZBA_GROUPID 0
+#define ZBA_BITMASK (1ULL << 35)
+#define ZBB_GROUPID 0
+#define ZBB_BITMASK (1ULL << 36)
+#define ZBC_GROUPID 0
+#define ZBC_BITMASK (1ULL << 37)
+#define ZBKB_GROUPID 0
+#define ZBKB_BITMASK (1ULL << 39)
+#define ZBKC_GROUPID 0
+#define ZBKC_BITMASK (1ULL << 41)
+#define ZBKX_GROUPID 0
+#define ZBKX_BITMASK (1ULL << 40)
+#define ZBS_GROUPID 0
+#define ZBS_BITMASK (1ULL << 38)
+#define ZFA_GROUPID 0
+#define ZFA_BITMASK (1ULL << 34)
+#define ZFH_GROUPID 0
+#define ZFH_BITMASK (1ULL << 33)
+#define ZFHMIN_GROUPID 0
+#define ZFHMIN_BITMASK (1ULL << 32)
+#define ZICBOZ_GROUPID 0
+#define ZICBOZ_BITMASK (1ULL << 26)
+#define ZICOND_GROUPID 0
+#define ZICOND_BITMASK (1ULL << 28)
+#define ZICSR_GROUPID 0
+#define ZICSR_BITMASK (1ULL << 27)
+#define ZIHINTNTL_GROUPID 0
+#define ZIHINTNTL_BITMASK (1ULL << 29)
+#define ZKND_GROUPID 0
+#define ZKND_BITMASK (1ULL << 42)
+#define ZKNE_GROUPID 0
+#define ZKNE_BITMASK (1ULL << 43)
+#define ZKNH_GROUPID 0
+#define ZKNH_BITMASK (1ULL << 44)
+#define ZKSED_GROUPID 0
+#define ZKSED_BITMASK (1ULL << 45)
+#define ZKSH_GROUPID 0
+#define ZKSH_BITMASK (1ULL << 46)
+#define ZKT_GROUPID 0
+#define ZKT_BITMASK (1ULL << 47)
+#define ZTSO_GROUPID 0
+#define ZTSO_BITMASK (1ULL << 30)
#define ZVBB_GROUPID 1
-#define ZVBB_BITMASK (1ULL << 46)
+#define ZVBB_BITMASK (1ULL << 4)
#define ZVBC_GROUPID 1
-#define ZVBC_BITMASK (1ULL << 47)
-#define ZVE32F_GROUPID 1
-#define ZVE32F_BITMASK (1ULL << 38)
-#define ZVE32X_GROUPID 1
-#define ZVE32X_BITMASK (1ULL << 37)
+#define ZVBC_BITMASK (1ULL << 5)
+#define ZVE32F_GROUPID 0
+#define ZVE32F_BITMASK (1ULL << 61)
+#define ZVE32X_GROUPID 0
+#define ZVE32X_BITMASK (1ULL << 60)
#define ZVE64D_GROUPID 1
-#define ZVE64D_BITMASK (1ULL << 41)
-#define ZVE64F_GROUPID 1
-#define ZVE64F_BITMASK (1ULL << 40)
-#define ZVE64X_GROUPID 1
-#define ZVE64X_BITMASK (1ULL << 39)
+#define ZVE64D_BITMASK (1ULL << 0)
+#define ZVE64F_GROUPID 0
+#define ZVE64F_BITMASK (1ULL << 63)
+#define ZVE64X_GROUPID 0
+#define ZVE64X_BITMASK (1ULL << 62)
#define ZVFH_GROUPID 1
-#define ZVFH_BITMASK (1ULL << 44)
+#define ZVFH_BITMASK (1ULL << 2)
#define ZVFHMIN_GROUPID 1
-#define ZVFHMIN_BITMASK (1ULL << 43)
+#define ZVFHMIN_BITMASK (1ULL << 1)
#define ZVKB_GROUPID 1
-#define ZVKB_BITMASK (1ULL << 45)
+#define ZVKB_BITMASK (1ULL << 3)
#define ZVKG_GROUPID 1
-#define ZVKG_BITMASK (1ULL << 48)
-#define ZVKN_GROUPID 1
-#define ZVKN_BITMASK (1ULL << 56)
+#define ZVKG_BITMASK (1ULL << 6)
#define ZVKNED_GROUPID 1
-#define ZVKNED_BITMASK (1ULL << 49)
-#define ZVKNG_GROUPID 1
-#define ZVKNG_BITMASK (1ULL << 57)
+#define ZVKNED_BITMASK (1ULL << 7)
#define ZVKNHA_GROUPID 1
-#define ZVKNHA_BITMASK (1ULL << 50)
+#define ZVKNHA_BITMASK (1ULL << 8)
#define ZVKNHB_GROUPID 1
-#define ZVKNHB_BITMASK (1ULL << 51)
-#define ZVKS_GROUPID 1
-#define ZVKS_BITMASK (1ULL << 58)
+#define ZVKNHB_BITMASK (1ULL << 9)
#define ZVKSED_GROUPID 1
-#define ZVKSED_BITMASK (1ULL << 52)
-#define ZVKSG_GROUPID 1
-#define ZVKSG_BITMASK (1ULL << 59)
+#define ZVKSED_BITMASK (1ULL << 10)
#define ZVKSH_GROUPID 1
-#define ZVKSH_BITMASK (1ULL << 53)
+#define ZVKSH_BITMASK (1ULL << 11)
#define ZVKT_GROUPID 1
-#define ZVKT_BITMASK (1ULL << 54)
-#define ZVL1024B_GROUPID 1
-#define ZVL1024B_BITMASK (1ULL << 30)
-#define ZVL128B_GROUPID 1
-#define ZVL128B_BITMASK (1ULL << 27)
-#define ZVL16384B_GROUPID 1
-#define ZVL16384B_BITMASK (1ULL << 34)
-#define ZVL2048B_GROUPID 1
-#define ZVL2048B_BITMASK (1ULL << 31)
-#define ZVL256B_GROUPID 1
-#define ZVL256B_BITMASK (1ULL << 28)
-#define ZVL32768B_GROUPID 1
-#define ZVL32768B_BITMASK (1ULL << 35)
-#define ZVL32B_GROUPID 1
-#define ZVL32B_BITMASK (1ULL << 25)
-#define ZVL4096B_GROUPID 1
-#define ZVL4096B_BITMASK (1ULL << 32)
-#define ZVL512B_GROUPID 1
-#define ZVL512B_BITMASK (1ULL << 29)
-#define ZVL64B_GROUPID 1
-#define ZVL64B_BITMASK (1ULL << 26)
-#define ZVL65536B_GROUPID 1
-#define ZVL65536B_BITMASK (1ULL << 36)
-#define ZVL8192B_GROUPID 1
-#define ZVL8192B_BITMASK (1ULL << 33)
+#define ZVKT_BITMASK (1ULL << 12)
+#define ZVL1024B_GROUPID 0
+#define ZVL1024B_BITMASK (1ULL << 53)
+#define ZVL128B_GROUPID 0
+#define ZVL128B_BITMASK (1ULL << 50)
+#define ZVL16384B_GROUPID 0
+#define ZVL16384B_BITMASK (1ULL << 57)
+#define ZVL2048B_GROUPID 0
+#define ZVL2048B_BITMASK (1ULL << 54)
+#define ZVL256B_GROUPID 0
+#define ZVL256B_BITMASK (1ULL << 51)
+#define ZVL32768B_GROUPID 0
+#define ZVL32768B_BITMASK (1ULL << 58)
+#define ZVL32B_GROUPID 0
+#define ZVL32B_BITMASK (1ULL << 48)
+#define ZVL4096B_GROUPID 0
+#define ZVL4096B_BITMASK (1ULL << 55)
+#define ZVL512B_GROUPID 0
+#define ZVL512B_BITMASK (1ULL << 52)
+#define ZVL64B_GROUPID 0
+#define ZVL64B_BITMASK (1ULL << 49)
+#define ZVL65536B_GROUPID 0
+#define ZVL65536B_BITMASK (1ULL << 59)
+#define ZVL8192B_GROUPID 0
+#define ZVL8192B_BITMASK (1ULL << 56)
#define HWPROBE_LENGTH 3
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