[llvm] [Pipelines] Perform mergefunc after constmerge (PR #92498)
YAMAMOTO Takashi via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 26 04:05:36 PDT 2024
https://github.com/yamt updated https://github.com/llvm/llvm-project/pull/92498
>From 1c8845a17bcad38b8baec73616ea13497d99fd1f Mon Sep 17 00:00:00 2001
From: YAMAMOTO Takashi <yamamoto at midokura.com>
Date: Fri, 17 May 2024 14:31:17 +0900
Subject: [PATCH 1/5] [Pipelines] Perform mergefunc after constmerge
Constmerge can fold switch jump tables, possibly making functions
identical again. It can help mergefunc.
On the otherhand, the opposite seems unlikely.
Fixes https://github.com/llvm/llvm-project/issues/92201
---
llvm/lib/Passes/PassBuilderPipelines.cpp | 9 +++++----
llvm/test/Other/new-pm-defaults.ll | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp
index 926515c9508a97..4fd5ee1946bb77 100644
--- a/llvm/lib/Passes/PassBuilderPipelines.cpp
+++ b/llvm/lib/Passes/PassBuilderPipelines.cpp
@@ -1527,10 +1527,6 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level,
if (EnableIROutliner)
MPM.addPass(IROutlinerPass());
- // Merge functions if requested.
- if (PTO.MergeFunctions)
- MPM.addPass(MergeFunctionsPass());
-
// Now we need to do some global optimization transforms.
// FIXME: It would seem like these should come first in the optimization
// pipeline and maybe be the bottom of the canonicalization pipeline? Weird
@@ -1538,6 +1534,11 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level,
MPM.addPass(GlobalDCEPass());
MPM.addPass(ConstantMergePass());
+ // Merge functions if requested. It has a better chance to merge functions
+ // after ConstantMerge folded jump tables.
+ if (PTO.MergeFunctions)
+ MPM.addPass(MergeFunctionsPass());
+
if (PTO.CallGraphProfile && !LTOPreLink)
MPM.addPass(CGProfilePass(LTOPhase == ThinOrFullLTOPhase::FullLTOPostLink ||
LTOPhase == ThinOrFullLTOPhase::ThinLTOPostLink));
diff --git a/llvm/test/Other/new-pm-defaults.ll b/llvm/test/Other/new-pm-defaults.ll
index 489aed40c190b4..588337c15625e6 100644
--- a/llvm/test/Other/new-pm-defaults.ll
+++ b/llvm/test/Other/new-pm-defaults.ll
@@ -281,9 +281,9 @@
; CHECK-HOT-COLD-SPLIT-NEXT: Running pass: HotColdSplittingPass
; CHECK-IR-OUTLINER-NEXT: Running pass: IROutlinerPass
; CHECK-IR-OUTLINER-NEXT: Running analysis: IRSimilarityAnalysis
-; CHECK-MERGE-FUNCS-NEXT: Running pass: MergeFunctionsPass
; CHECK-O-NEXT: Running pass: GlobalDCEPass
; CHECK-O-NEXT: Running pass: ConstantMergePass
+; CHECK-MERGE-FUNCS-NEXT: Running pass: MergeFunctionsPass
; CHECK-DEFAULT-NEXT: Running pass: CGProfilePass
; CHECK-DEFAULT-NEXT: Running pass: RelLookupTableConverterPass
; CHECK-LTO-NOT: Running pass: RelLookupTableConverterPass
>From a6d30c85d21401dde8a0a75d629c45bac8fadbd2 Mon Sep 17 00:00:00 2001
From: YAMAMOTO Takashi <yamamoto at midokura.com>
Date: Wed, 26 Jun 2024 18:49:45 +0900
Subject: [PATCH 2/5] add a few tests
---
.../PhaseOrdering/X86/merge-functions2.ll | 67 +++++++++++++++++++
.../PhaseOrdering/X86/merge-functions3.ll | 47 +++++++++++++
2 files changed, 114 insertions(+)
create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
create mode 100644 llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
new file mode 100644
index 00000000000000..5d650d5f080bac
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
@@ -0,0 +1,67 @@
+; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
+
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx12.0.0"
+
+; Function Attrs: noinline nounwind optsize ssp uwtable
+define i32 @f(i32 noundef %x) #0 {
+; CHECK-LABEL: @f(
+entry:
+ %x.addr = alloca i32, align 4
+ store i32 %x, ptr %x.addr, align 4, !tbaa !5
+ %0 = load i32, ptr %x.addr, align 4, !tbaa !5
+ switch i32 %0, label %sw.default [
+ i32 0, label %sw.bb
+ i32 2, label %sw.bb
+ i32 4, label %sw.bb
+ i32 6, label %sw.bb
+ i32 7, label %sw.bb
+ ]
+
+sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
+ store i32 1, ptr %x.addr, align 4, !tbaa !5
+ br label %sw.epilog
+
+sw.default: ; preds = %entry
+ store i32 0, ptr %x.addr, align 4, !tbaa !5
+ br label %sw.epilog
+
+sw.epilog: ; preds = %sw.default, %sw.bb
+ %1 = load i32, ptr %x.addr, align 4, !tbaa !5
+ ret i32 %1
+}
+
+; Function Attrs: noinline nounwind optsize ssp uwtable
+define i32 @g(i32 noundef %x) #0 {
+; CHECK-LABEL: @g(
+; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT: ret i32 [[TMP2]]
+entry:
+ %x.addr = alloca i32, align 4
+ store i32 %x, ptr %x.addr, align 4, !tbaa !5
+ %0 = load i32, ptr %x.addr, align 4, !tbaa !5
+ switch i32 %0, label %sw.default [
+ i32 0, label %sw.bb
+ i32 2, label %sw.bb
+ i32 4, label %sw.bb
+ i32 6, label %sw.bb
+ i32 7, label %sw.bb
+ ]
+
+sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
+ store i32 1, ptr %x.addr, align 4, !tbaa !5
+ br label %sw.epilog
+
+sw.default: ; preds = %entry
+ store i32 0, ptr %x.addr, align 4, !tbaa !5
+ br label %sw.epilog
+
+sw.epilog: ; preds = %sw.default, %sw.bb
+ %1 = load i32, ptr %x.addr, align 4, !tbaa !5
+ ret i32 %1
+}
+
+!5 = !{!6, !6, i64 0}
+!6 = !{!"int", !7, i64 0}
+!7 = !{!"omnipotent char", !8, i64 0}
+!8 = !{!"Simple C/C++ TBAA"}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
new file mode 100644
index 00000000000000..bce8f08ceda5e0
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
@@ -0,0 +1,47 @@
+; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
+
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx12.0.0"
+
+ at switch.table.f = private unnamed_addr constant [8 x i32] [i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 1], align 4
+ at switch.table.g = private unnamed_addr constant [8 x i32] [i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 1], align 4
+
+; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind optsize ssp willreturn memory(none) uwtable
+define range(i32 0, 2) i32 @f(i32 noundef %x) local_unnamed_addr #0 {
+; CHECK-LABEL: @f(
+entry:
+ %0 = icmp ult i32 %x, 8
+ br i1 %0, label %switch.lookup, label %sw.epilog
+
+switch.lookup: ; preds = %entry
+ %1 = zext nneg i32 %x to i64
+ %switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.f, i64 0, i64 %1
+ %switch.load = load i32, ptr %switch.gep, align 4
+ br label %sw.epilog
+
+sw.epilog: ; preds = %entry, %switch.lookup
+ %x.addr.0 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %entry ]
+ ret i32 %x.addr.0
+}
+
+; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind optsize ssp willreturn memory(none) uwtable
+define range(i32 0, 2) i32 @g(i32 noundef %x) local_unnamed_addr #0 {
+; CHECK-LABEL: @g(
+; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT: ret i32 [[TMP2]]
+entry:
+ %0 = icmp ult i32 %x, 8
+ br i1 %0, label %switch.lookup, label %sw.epilog
+
+switch.lookup: ; preds = %entry
+ %1 = zext nneg i32 %x to i64
+ %switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.g, i64 0, i64 %1
+ %switch.load = load i32, ptr %switch.gep, align 4
+ br label %sw.epilog
+
+sw.epilog: ; preds = %entry, %switch.lookup
+ %x.addr.0 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %entry ]
+ ret i32 %x.addr.0
+}
+
+attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind optsize ssp willreturn memory(none) uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cmov,+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "tune-cpu"="generic" }
>From 174dd173efb1f0e83387279a980be7997c40f014 Mon Sep 17 00:00:00 2001
From: YAMAMOTO Takashi <yamamoto at midokura.com>
Date: Wed, 26 Jun 2024 20:00:13 +0900
Subject: [PATCH 3/5] drop tbaa metadata
---
.../PhaseOrdering/X86/merge-functions2.ll | 25 ++++++++-----------
1 file changed, 10 insertions(+), 15 deletions(-)
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
index 5d650d5f080bac..09ee2df5163abf 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
@@ -8,8 +8,8 @@ define i32 @f(i32 noundef %x) #0 {
; CHECK-LABEL: @f(
entry:
%x.addr = alloca i32, align 4
- store i32 %x, ptr %x.addr, align 4, !tbaa !5
- %0 = load i32, ptr %x.addr, align 4, !tbaa !5
+ store i32 %x, ptr %x.addr, align 4
+ %0 = load i32, ptr %x.addr, align 4
switch i32 %0, label %sw.default [
i32 0, label %sw.bb
i32 2, label %sw.bb
@@ -19,15 +19,15 @@ entry:
]
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
- store i32 1, ptr %x.addr, align 4, !tbaa !5
+ store i32 1, ptr %x.addr, align 4
br label %sw.epilog
sw.default: ; preds = %entry
- store i32 0, ptr %x.addr, align 4, !tbaa !5
+ store i32 0, ptr %x.addr, align 4
br label %sw.epilog
sw.epilog: ; preds = %sw.default, %sw.bb
- %1 = load i32, ptr %x.addr, align 4, !tbaa !5
+ %1 = load i32, ptr %x.addr, align 4
ret i32 %1
}
@@ -38,8 +38,8 @@ define i32 @g(i32 noundef %x) #0 {
; CHECK-NEXT: ret i32 [[TMP2]]
entry:
%x.addr = alloca i32, align 4
- store i32 %x, ptr %x.addr, align 4, !tbaa !5
- %0 = load i32, ptr %x.addr, align 4, !tbaa !5
+ store i32 %x, ptr %x.addr, align 4
+ %0 = load i32, ptr %x.addr, align 4
switch i32 %0, label %sw.default [
i32 0, label %sw.bb
i32 2, label %sw.bb
@@ -49,19 +49,14 @@ entry:
]
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
- store i32 1, ptr %x.addr, align 4, !tbaa !5
+ store i32 1, ptr %x.addr, align 4
br label %sw.epilog
sw.default: ; preds = %entry
- store i32 0, ptr %x.addr, align 4, !tbaa !5
+ store i32 0, ptr %x.addr, align 4
br label %sw.epilog
sw.epilog: ; preds = %sw.default, %sw.bb
- %1 = load i32, ptr %x.addr, align 4, !tbaa !5
+ %1 = load i32, ptr %x.addr, align 4
ret i32 %1
}
-
-!5 = !{!6, !6, i64 0}
-!6 = !{!"int", !7, i64 0}
-!7 = !{!"omnipotent char", !8, i64 0}
-!8 = !{!"Simple C/C++ TBAA"}
>From 2d3dc73cd7ac41a05fa69bffadb367d1040ac060 Mon Sep 17 00:00:00 2001
From: YAMAMOTO Takashi <yamamoto at midokura.com>
Date: Wed, 26 Jun 2024 20:00:56 +0900
Subject: [PATCH 4/5] drop attributes
---
llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
index bce8f08ceda5e0..8e875d7fe23605 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
@@ -43,5 +43,3 @@ sw.epilog: ; preds = %entry, %switch.look
%x.addr.0 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %entry ]
ret i32 %x.addr.0
}
-
-attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind optsize ssp willreturn memory(none) uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cmov,+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "tune-cpu"="generic" }
>From 003cb54982a55ce52b753da5fd511625b284de39 Mon Sep 17 00:00:00 2001
From: YAMAMOTO Takashi <yamamoto at midokura.com>
Date: Wed, 26 Jun 2024 20:04:40 +0900
Subject: [PATCH 5/5] apply utils/update_test_checks.py
---
.../PhaseOrdering/X86/merge-functions2.ll | 42 +++++++++++++------
.../PhaseOrdering/X86/merge-functions3.ll | 22 ++++++++--
2 files changed, 48 insertions(+), 16 deletions(-)
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
index 09ee2df5163abf..aea78afa64d2ee 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
@@ -5,17 +6,30 @@ target triple = "x86_64-apple-macosx12.0.0"
; Function Attrs: noinline nounwind optsize ssp uwtable
define i32 @f(i32 noundef %x) #0 {
-; CHECK-LABEL: @f(
+; CHECK-LABEL: define range(i32 0, 2) i32 @f(
+; CHECK-SAME: i32 noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 8
+; CHECK-NEXT: br i1 [[TMP0]], label %[[SWITCH_LOOKUP:.*]], label %[[SW_EPILOG:.*]]
+; CHECK: [[SWITCH_LOOKUP]]:
+; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[X]] to i64
+; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.g, i64 0, i64 [[TMP1]]
+; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
+; CHECK-NEXT: br label %[[SW_EPILOG]]
+; CHECK: [[SW_EPILOG]]:
+; CHECK-NEXT: [[X_ADDR_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], %[[SWITCH_LOOKUP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: ret i32 [[X_ADDR_0]]
+;
entry:
%x.addr = alloca i32, align 4
store i32 %x, ptr %x.addr, align 4
%0 = load i32, ptr %x.addr, align 4
switch i32 %0, label %sw.default [
- i32 0, label %sw.bb
- i32 2, label %sw.bb
- i32 4, label %sw.bb
- i32 6, label %sw.bb
- i32 7, label %sw.bb
+ i32 0, label %sw.bb
+ i32 2, label %sw.bb
+ i32 4, label %sw.bb
+ i32 6, label %sw.bb
+ i32 7, label %sw.bb
]
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
@@ -33,19 +47,21 @@ sw.epilog: ; preds = %sw.default, %sw.bb
; Function Attrs: noinline nounwind optsize ssp uwtable
define i32 @g(i32 noundef %x) #0 {
-; CHECK-LABEL: @g(
-; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]]
+; CHECK-LABEL: define range(i32 0, 2) i32 @g(
+; CHECK-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]]
; CHECK-NEXT: ret i32 [[TMP2]]
+;
entry:
%x.addr = alloca i32, align 4
store i32 %x, ptr %x.addr, align 4
%0 = load i32, ptr %x.addr, align 4
switch i32 %0, label %sw.default [
- i32 0, label %sw.bb
- i32 2, label %sw.bb
- i32 4, label %sw.bb
- i32 6, label %sw.bb
- i32 7, label %sw.bb
+ i32 0, label %sw.bb
+ i32 2, label %sw.bb
+ i32 4, label %sw.bb
+ i32 6, label %sw.bb
+ i32 7, label %sw.bb
]
sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
index 8e875d7fe23605..881f4b97163e42 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
@@ -8,7 +9,20 @@ target triple = "x86_64-apple-macosx12.0.0"
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind optsize ssp willreturn memory(none) uwtable
define range(i32 0, 2) i32 @f(i32 noundef %x) local_unnamed_addr #0 {
-; CHECK-LABEL: @f(
+; CHECK-LABEL: define range(i32 0, 2) i32 @f(
+; CHECK-SAME: i32 noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 8
+; CHECK-NEXT: br i1 [[TMP0]], label %[[SWITCH_LOOKUP:.*]], label %[[SW_EPILOG:.*]]
+; CHECK: [[SWITCH_LOOKUP]]:
+; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[X]] to i64
+; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.g, i64 0, i64 [[TMP1]]
+; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
+; CHECK-NEXT: br label %[[SW_EPILOG]]
+; CHECK: [[SW_EPILOG]]:
+; CHECK-NEXT: [[X_ADDR_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], %[[SWITCH_LOOKUP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: ret i32 [[X_ADDR_0]]
+;
entry:
%0 = icmp ult i32 %x, 8
br i1 %0, label %switch.lookup, label %sw.epilog
@@ -26,9 +40,11 @@ sw.epilog: ; preds = %entry, %switch.look
; Function Attrs: mustprogress nofree noinline norecurse nosync nounwind optsize ssp willreturn memory(none) uwtable
define range(i32 0, 2) i32 @g(i32 noundef %x) local_unnamed_addr #0 {
-; CHECK-LABEL: @g(
-; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]]
+; CHECK-LABEL: define range(i32 0, 2) i32 @g(
+; CHECK-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] {
+; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]]
; CHECK-NEXT: ret i32 [[TMP2]]
+;
entry:
%0 = icmp ult i32 %x, 8
br i1 %0, label %switch.lookup, label %sw.epilog
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