[llvm] 28a3fbb - [X86][test] Pre-commit test for disabling NDD2NonNDD transform for 8/16-bit ops
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 26 00:08:30 PDT 2024
Author: Shengchen Kan
Date: 2024-06-26T15:07:53+08:00
New Revision: 28a3fbbe8c6cd5b92fb0a2a3cc21a836a381e086
URL: https://github.com/llvm/llvm-project/commit/28a3fbbe8c6cd5b92fb0a2a3cc21a836a381e086
DIFF: https://github.com/llvm/llvm-project/commit/28a3fbbe8c6cd5b92fb0a2a3cc21a836a381e086.diff
LOG: [X86][test] Pre-commit test for disabling NDD2NonNDD transform for 8/16-bit ops
Added:
Modified:
llvm/test/CodeGen/X86/apx/compress-evex.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/apx/compress-evex.mir b/llvm/test/CodeGen/X86/apx/compress-evex.mir
index 5a59ab0f8a9d0..7723cac8eb326 100644
--- a/llvm/test/CodeGen/X86/apx/compress-evex.mir
+++ b/llvm/test/CodeGen/X86/apx/compress-evex.mir
@@ -127,3 +127,14 @@ body: |
$rbx = CFCMOV64rm_ND $rbx, $rax, 1, $noreg, 24, $noreg, 8, implicit $eflags
RET64 $rax
...
+---
+name: no_convert_8bit_16bit
+body: |
+ bb.0.entry:
+ liveins: $di, $si, $ax
+ ; CHECK: addb %sil, %dil # EVEX TO LEGACY Compression encoding: [0x40,0x00,0xf7]
+ ; CHECK: xorw %di, %ax # EVEX TO LEGACY Compression encoding: [0x66,0x31,0xf8]
+ $dil = ADD8rr_ND $dil, killed $sil, implicit-def dead $eflags
+ $ax = XOR16rr_ND $ax, killed $di, implicit-def dead $eflags
+ RET64 $rax
+...
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