[llvm] [PowerPC][AIX] Emit PowerPC version for XCOFF (PR #95510)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 23:05:09 PDT 2024
https://github.com/EsmeYi updated https://github.com/llvm/llvm-project/pull/95510
>From 5a9d0e3832d8fc65689e8971a3bdef22b06a9dac Mon Sep 17 00:00:00 2001
From: esmeyi <esme.yi at ibm.com>
Date: Fri, 14 Jun 2024 02:36:44 -0400
Subject: [PATCH 1/7] Emit PowerPC version for XCOFF.
---
llvm/include/llvm/BinaryFormat/XCOFF.h | 18 +++++-
llvm/include/llvm/MC/MCAssembler.h | 5 ++
llvm/include/llvm/MC/MCObjectStreamer.h | 1 +
llvm/include/llvm/MC/MCStreamer.h | 3 +
llvm/lib/BinaryFormat/XCOFF.cpp | 14 +++++
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 5 ++
llvm/lib/MC/MCAsmStreamer.cpp | 9 +++
llvm/lib/MC/MCObjectStreamer.cpp | 4 ++
llvm/lib/MC/MCStreamer.cpp | 1 +
llvm/lib/MC/XCOFFObjectWriter.cpp | 7 +--
llvm/test/CodeGen/PowerPC/aix-extern-weak.ll | 3 +-
llvm/test/CodeGen/PowerPC/aix-extern.ll | 3 +-
llvm/test/CodeGen/PowerPC/aix-filename-c.ll | 63 ++++++++++++++++---
llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll | 7 +--
llvm/test/CodeGen/PowerPC/aix-filename-f.ll | 7 +--
llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll | 2 +-
.../CodeGen/PowerPC/aix-llvm-intrinsic.ll | 3 +-
.../PowerPC/aix-tls-xcoff-reloc-large.ll | 2 +-
.../CodeGen/PowerPC/aix-tls-xcoff-reloc.ll | 2 +-
.../PowerPC/aix-tls-xcoff-variables.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-weak.ll | 3 +-
llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 8 +--
llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 3 +-
llvm/test/DebugInfo/XCOFF/empty.ll | 2 +
llvm/test/DebugInfo/XCOFF/explicit-section.ll | 1 +
.../test/DebugInfo/XCOFF/function-sections.ll | 1 +
.../llvm-readobj/XCOFF/symbols-invalid.test | 2 +-
.../tools/llvm-readobj/XCOFF/symbols.test | 2 +-
.../tools/llvm-readobj/XCOFF/symbols64.test | 2 +-
.../tools/yaml2obj/XCOFF/aux-symbols.yaml | 12 ++--
llvm/tools/llvm-readobj/XCOFFDumper.cpp | 15 ++++-
31 files changed, 159 insertions(+), 53 deletions(-)
diff --git a/llvm/include/llvm/BinaryFormat/XCOFF.h b/llvm/include/llvm/BinaryFormat/XCOFF.h
index bbcd8a4f29ae9..5e8d30b991f45 100644
--- a/llvm/include/llvm/BinaryFormat/XCOFF.h
+++ b/llvm/include/llvm/BinaryFormat/XCOFF.h
@@ -334,9 +334,20 @@ enum CFileLangId : uint8_t {
};
enum CFileCpuId : uint8_t {
- TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
- TCPU_COM = 3, ///< POWER and PowerPC architecture common.
- TCPU_970 = 19 ///< PPC970 - PowerPC 64-bit architecture.
+ TCPU_INVALID = 0, ///< Invalid id - assumes POWER for old objects.
+ TCPU_PPC = 1, ///< PowerPC common architecture 32 bit mode.
+ TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
+ TCPU_COM = 3, ///< POWER and PowerPC architecture common.
+ TCPU_PWR = 4, ///< POWER common architecture objects.
+ TCPU_PWR5 = 18, ///< PWR5 - PowerPC 64-bit architecture.
+ TCPU_970 = 19, ///< PPC970 - PowerPC 64-bit architecture.
+ TCPU_PWR6 = 20, ///< PWR6 - PowerPC 64-bit architecture.
+ TCPU_PWR5X = 22, ///< PWR5+ - PowerPC 64-bit architecture.
+ TCPU_PWR6E = 23, ///< PWR6E - PowerPC 64-bit architecture.
+ TCPU_PWR7 = 24, ///< PWR7 - PowerPC 64-bit architecture.
+ TCPU_PWR8 = 25, ///< PWR8 - PowerPC 64-bit architecture.
+ TCPU_PWR9 = 26, ///< PWR9 - PowerPC 64-bit architecture.
+ TCPU_PWR10 = 27, ///< PWR10 - PowerPC 64-bit architecture.
};
enum SymbolAuxType : uint8_t {
@@ -468,6 +479,7 @@ enum ExtendedTBTableFlag : uint8_t {
StringRef getNameForTracebackTableLanguageId(TracebackTable::LanguageID LangId);
SmallString<32> getExtendedTBTableFlagString(uint8_t Flag);
+XCOFF::CFileCpuId getCpuID(StringRef CPU);
struct CsectProperties {
CsectProperties(StorageMappingClass SMC, SymbolType ST)
diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h
index 914c7506e754b..45f4befeb84d5 100644
--- a/llvm/include/llvm/MC/MCAssembler.h
+++ b/llvm/include/llvm/MC/MCAssembler.h
@@ -135,6 +135,8 @@ class MCAssembler {
std::vector<std::pair<std::string, size_t>> FileNames;
// Optional compiler version.
std::string CompilerVersion;
+ // PPC CPU type.
+ StringRef CPU;
MCDwarfLineTableParams LTParams;
@@ -490,6 +492,9 @@ class MCAssembler {
}
StringRef getCompilerVersion() { return CompilerVersion; }
+ void setCPU(StringRef TargetCPU) { CPU = TargetCPU; }
+ StringRef getCPU() { return CPU; }
+
/// Write the necessary bundle padding to \p OS.
/// Expects a fragment \p F containing instructions and its size \p FSize.
void writeFragmentPadding(raw_ostream &OS, const MCEncodedFragment &F,
diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h
index c0a337f5ea45e..c3d44e51e98db 100644
--- a/llvm/include/llvm/MC/MCObjectStreamer.h
+++ b/llvm/include/llvm/MC/MCObjectStreamer.h
@@ -203,6 +203,7 @@ class MCObjectStreamer : public MCStreamer {
void emitFileDirective(StringRef Filename) override;
void emitFileDirective(StringRef Filename, StringRef CompilerVersion,
StringRef TimeStamp, StringRef Description) override;
+ void emitMachineDirective(StringRef CPU) override;
void emitAddrsig() override;
void emitAddrsigSym(const MCSymbol *Sym) override;
diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h
index b7468cf70a664..fa29c1dd5033d 100644
--- a/llvm/include/llvm/MC/MCStreamer.h
+++ b/llvm/include/llvm/MC/MCStreamer.h
@@ -908,6 +908,9 @@ class MCStreamer {
virtual void emitFileDirective(StringRef Filename, StringRef CompilerVersion,
StringRef TimeStamp, StringRef Description);
+ // Emit '.machine "CPU"' assembler diretive.
+ virtual void emitMachineDirective(StringRef CPU);
+
/// Emit the "identifiers" directive. This implements the
/// '.ident "version foo"' assembler directive.
virtual void emitIdent(StringRef IdentString) {}
diff --git a/llvm/lib/BinaryFormat/XCOFF.cpp b/llvm/lib/BinaryFormat/XCOFF.cpp
index 6b11ab2ff96bc..f2e3b2e82f950 100644
--- a/llvm/lib/BinaryFormat/XCOFF.cpp
+++ b/llvm/lib/BinaryFormat/XCOFF.cpp
@@ -9,6 +9,7 @@
#include "llvm/BinaryFormat/XCOFF.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/Errc.h"
#include "llvm/Support/Error.h"
@@ -107,6 +108,19 @@ StringRef XCOFF::getNameForTracebackTableLanguageId(
}
#undef LANG_CASE
+XCOFF::CFileCpuId XCOFF::getCpuID(StringRef CPU) {
+ return StringSwitch<XCOFF::CFileCpuId>(CPU)
+ .Case("pwr4", XCOFF::TCPU_PWR)
+ .Case("pwr5", XCOFF::TCPU_PWR5)
+ .Case("pwr6", XCOFF::TCPU_PWR6)
+ .Case("pwr5x", XCOFF::TCPU_PWR5X)
+ .Case("pwr7", XCOFF::TCPU_PWR7)
+ .Case("pwr8", XCOFF::TCPU_PWR8)
+ .Case("pwr9", XCOFF::TCPU_PWR9)
+ .Case("pwr10", XCOFF::TCPU_PWR10)
+ .Default(XCOFF::TCPU_PWR7);
+}
+
Expected<SmallString<32>> XCOFF::parseParmsType(uint32_t Value,
unsigned FixedParmsNum,
unsigned FloatingParmsNum) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 3580d484b7ddd..f9a7c37b70bf2 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -517,6 +517,11 @@ bool AsmPrinter::doInitialization(Module &M) {
// On AIX, emit bytes for llvm.commandline metadata after .file so that the
// C_INFO symbol is preserved if any csect is kept by the linker.
if (TM.getTargetTriple().isOSBinFormatXCOFF()) {
+ // Emit .machine directive on AIX.
+ StringRef TargetCPU =
+ TM.getTargetCPU().empty() ? "pwr7" : TM.getTargetCPU();
+ OutStreamer->emitMachineDirective(TargetCPU);
+
emitModuleCommandLines(M);
// Now we can generate section information.
OutStreamer->initSections(false, *TM.getMCSubtargetInfo());
diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
index f257d0d9e83f7..4b6c52eb9f68a 100644
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -272,6 +272,9 @@ class MCAsmStreamer final : public MCStreamer {
void emitFileDirective(StringRef Filename) override;
void emitFileDirective(StringRef Filename, StringRef CompilerVersion,
StringRef TimeStamp, StringRef Description) override;
+
+ void emitMachineDirective(StringRef CPU) override;
+
Expected<unsigned> tryEmitDwarfFileDirective(
unsigned FileNo, StringRef Directory, StringRef Filename,
std::optional<MD5::MD5Result> Checksum = std::nullopt,
@@ -1610,6 +1613,12 @@ void MCAsmStreamer::emitFileDirective(StringRef Filename,
EmitEOL();
}
+void MCAsmStreamer::emitMachineDirective(StringRef CPU) {
+ OS << "\t.machine\t";
+ PrintQuotedString(CPU, OS);
+ EmitEOL();
+}
+
void MCAsmStreamer::printDwarfFileDirective(
unsigned FileNo, StringRef Directory, StringRef Filename,
std::optional<MD5::MD5Result> Checksum, std::optional<StringRef> Source,
diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp
index bf1ce76cdc14b..80c1a8920177f 100644
--- a/llvm/lib/MC/MCObjectStreamer.cpp
+++ b/llvm/lib/MC/MCObjectStreamer.cpp
@@ -902,6 +902,10 @@ void MCObjectStreamer::emitFileDirective(StringRef Filename,
// with the integrated assembler.
}
+void MCObjectStreamer::emitMachineDirective(StringRef CPU) {
+ getAssembler().setCPU(CPU);
+}
+
void MCObjectStreamer::emitAddrsig() {
getAssembler().getWriter().emitAddrsigSection();
}
diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp
index 199d865ea3496..c248cc5002ea5 100644
--- a/llvm/lib/MC/MCStreamer.cpp
+++ b/llvm/lib/MC/MCStreamer.cpp
@@ -1171,6 +1171,7 @@ void MCStreamer::emitFileDirective(StringRef Filename,
StringRef CompilerVersion,
StringRef TimeStamp, StringRef Description) {
}
+void MCStreamer::emitMachineDirective(StringRef CPU) {}
void MCStreamer::emitCOFFSymbolStorageClass(int StorageClass) {
llvm_unreachable("this directive only supported on COFF targets");
}
diff --git a/llvm/lib/MC/XCOFFObjectWriter.cpp b/llvm/lib/MC/XCOFFObjectWriter.cpp
index a7c3818d598b7..c059b98212f62 100644
--- a/llvm/lib/MC/XCOFFObjectWriter.cpp
+++ b/llvm/lib/MC/XCOFFObjectWriter.cpp
@@ -1193,11 +1193,8 @@ void XCOFFObjectWriter::writeSymbolTable(MCAssembler &Asm,
LangID = XCOFF::TB_Fortran;
else
LangID = XCOFF::TB_CPLUSPLUS;
- uint8_t CpuID;
- if (is64Bit())
- CpuID = XCOFF::TCPU_PPC64;
- else
- CpuID = XCOFF::TCPU_COM;
+
+ uint8_t CpuID = XCOFF::getCpuID(Asm.getCPU());
int NumberOfFileAuxEntries = 1;
if (!Vers.empty())
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
index ea61fdb022b5c..ab62cd95ae2a4 100644
--- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -69,8 +69,7 @@ declare extern_weak void @foo_ext_weak(ptr)
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll
index b4366dddedb2f..825e30242ed50 100644
--- a/llvm/test/CodeGen/PowerPC/aix-extern.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll
@@ -92,8 +92,7 @@ declare i32 @bar_extern(ptr)
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
index c4202a0c58cee..dd342c00176f3 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
@@ -1,12 +1,57 @@
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
-; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s
-; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
-; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr9 < %s | FileCheck --check-prefixes=ASM %s
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr9 -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ32 %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr9 -filetype=obj -o %t64.o < %s
+; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ64 %s
source_filename = "1.c"
-; OBJ: Name: .file
-; OBJ: Source Language ID: TB_C (0x0)
-; OBJ32: CPU Version ID: TCPU_COM (0x3)
-; OBJ64: CPU Version ID: TCPU_PPC64 (0x2)
-; OBJ: Name: 1.c
+; ASM: .file "1.c",,"LLVM version 19.0.0git"
+; ASM-NEXT: .machine "pwr9"
+; ASM-NEXT: .csect ..text..[PR],5
+; ASM-NEXT: .rename ..text..[PR],""
+
+; OBJ32: Symbol {
+; OBJ32-NEXT: Index: 0
+; OBJ32-NEXT: Name: .file
+; OBJ32-NEXT: Value (SymbolTableIndex): 0x0
+; OBJ32-NEXT: Section: N_DEBUG
+; OBJ32-NEXT: Source Language ID: TB_C (0x0)
+; OBJ32-NEXT: CPU Version ID: TCPU_PWR9 (0x1A)
+; OBJ32-NEXT: StorageClass: C_FILE (0x67)
+; OBJ32-NEXT: NumberOfAuxEntries: 2
+; OBJ32-NEXT: File Auxiliary Entry {
+; OBJ32-NEXT: Index: 1
+; OBJ32-NEXT: Name: 1.c
+; OBJ32-NEXT: Type: XFT_FN (0x0)
+; OBJ32-NEXT: }
+; OBJ32-NEXT: File Auxiliary Entry {
+; OBJ32-NEXT: Index: 2
+; OBJ32-NEXT: Name: LLVM version 19.0.0git
+; OBJ32-NEXT: Type: XFT_CV (0x2)
+; OBJ32-NEXT: }
+; OBJ32-NEXT: }
+
+; OBJ64: Symbol {
+; OBJ64-NEXT: Index: 0
+; OBJ64-NEXT: Name: .file
+; OBJ64-NEXT: Value (SymbolTableIndex): 0x0
+; OBJ64-NEXT: Section: N_DEBUG
+; OBJ64-NEXT: Source Language ID: TB_C (0x0)
+; OBJ64-NEXT: CPU Version ID: TCPU_PWR9 (0x1A)
+; OBJ64-NEXT: StorageClass: C_FILE (0x67)
+; OBJ64-NEXT: NumberOfAuxEntries: 2
+; OBJ64-NEXT: File Auxiliary Entry {
+; OBJ64-NEXT: Index: 1
+; OBJ64-NEXT: Name: 1.c
+; OBJ64-NEXT: Type: XFT_FN (0x0)
+; OBJ64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
+; OBJ64-NEXT: }
+; OBJ64-NEXT: File Auxiliary Entry {
+; OBJ64-NEXT: Index: 2
+; OBJ64-NEXT: Name: LLVM version 19.0.0git
+; OBJ64-NEXT: Type: XFT_CV (0x2)
+; OBJ64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
+; OBJ64-NEXT: }
+; OBJ64-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
index 802281b6c1eaa..873619d20cd2c 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
@@ -1,12 +1,11 @@
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
-; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s
+; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
-; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s
+; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ %s
source_filename = "1.cpp"
; OBJ: Name: .file
; OBJ: Source Language ID: TB_CPLUSPLUS (0x9)
-; OBJ32: CPU Version ID: TCPU_COM (0x3)
-; OBJ64: CPU Version ID: TCPU_PPC64 (0x2)
+; OBJ: CPU Version ID: TCPU_PWR7 (0x18)
; OBJ: Name: 1.cpp
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
index 99036bde702d6..1167148d21a7f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
@@ -1,12 +1,11 @@
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
-; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s
+; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=OBJ %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
-; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s
+; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=OBJ %s
source_filename = "1.f95"
; OBJ: Name: .file
; OBJ: Source Language ID: TB_Fortran (0x1)
-; OBJ32: CPU Version ID: TCPU_COM (0x3)
-; OBJ64: CPU Version ID: TCPU_PPC64 (0x2)
+; OBJ: CPU Version ID: TCPU_PWR7 (0x18)
; OBJ: Name: 1.f95
diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
index 4cca1b4d6f7ba..50221acc2b3ad 100644
--- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
@@ -17,7 +17,7 @@ entry:
; CHECK-NEXT: Value (SymbolTableIndex): 0x0
; CHECK-NEXT: Section: N_DEBUG
; CHECK-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECK-NEXT: CPU Version ID: TCPU_COM (0x3)
+; CHECK-NEXT: CPU Version ID: TCPU_PWR7 (0x18)
; CHECK-NEXT: StorageClass: C_FILE (0x67)
; CHECK-NEXT: NumberOfAuxEntries: 2
; CHECK-NEXT: File Auxiliary Entry {
diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
index 50677f36e3f7a..dc849c4f8933f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
@@ -44,8 +44,7 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
index 63d927391936c..d943d9bd6cf10 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
@@ -215,7 +215,7 @@ entry:
; SYM-NEXT: Value (SymbolTableIndex): 0x0
; SYM-NEXT: Section: N_DEBUG
; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM-NEXT: CPU Version ID: TCPU_COM (0x3)
+; SYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
; SYM-NEXT: StorageClass: C_FILE (0x67)
; SYM-NEXT: NumberOfAuxEntries: 2
; SYM-NEXT: File Auxiliary Entry {
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
index c17b038a6960c..db1e770e04a1e 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
@@ -176,7 +176,7 @@ entry:
; SYM-NEXT: Value (SymbolTableIndex): 0x0
; SYM-NEXT: Section: N_DEBUG
; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM-NEXT: CPU Version ID: TCPU_COM (0x3)
+; SYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
; SYM-NEXT: StorageClass: C_FILE (0x67)
; SYM-NEXT: NumberOfAuxEntries: 2
; SYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
index f9a1a61617761..3c84aa1225d2e 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
@@ -70,7 +70,7 @@
; SYMS-NEXT: Value (SymbolTableIndex): 0x0
; SYMS-NEXT: Section: N_DEBUG
; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYMS-NEXT: CPU Version ID: TCPU_COM (0x3)
+; SYMS-NEXT: CPU Version ID: TCPU_PWR7 (0x18)
; SYMS-NEXT: StorageClass: C_FILE (0x67)
; SYMS-NEXT: NumberOfAuxEntries: 2
; SYMS: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll
index 7bf80ad19e9e0..3387eef8e43cb 100644
--- a/llvm/test/CodeGen/PowerPC/aix-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll
@@ -104,8 +104,7 @@ entry:
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3)
-; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
index de937386b8b7d..e28751f10a12f 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
@@ -45,8 +45,9 @@
; CHECK-NOT: .toc
-; CHECK: .file
-; CHECK-NEXT: .csect ..text..[PR],5
+; CHECK: .file
+; CHECK-NEXT: .machine "pwr7"
+; CHECK-NEXT: .csect ..text..[PR],5
; CHECK: .csect .data[RW],5
; CHECK-NEXT: .globl ivar
@@ -212,8 +213,7 @@
; SYMS-NEXT: Value (SymbolTableIndex): 0x0
; SYMS-NEXT: Section: N_DEBUG
; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYMS32-NEXT: CPU Version ID: TCPU_COM (0x3)
-; SYMS64-NEXT: CPU Version ID: TCPU_PPC64 (0x2)
+; SYMS-NEXT: CPU Version ID: TCPU_PWR7 (0x18)
; SYMS-NEXT: StorageClass: C_FILE (0x67)
; SYMS-NEXT: NumberOfAuxEntries: 2
; SYMS-NEXT: File Auxiliary Entry {
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
index 6599debbd41b4..541b3b1c19c05 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -163,8 +163,7 @@ declare i32 @bar(i32)
; SYM-NEXT: Value (SymbolTableIndex): 0x0
; SYM-NEXT: Section: N_DEBUG
; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM32-NEXT: CPU Version ID: TCPU_COM (0x3)
-; SYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2)
+; SYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
; SYM-NEXT: StorageClass: C_FILE (0x67)
; SYM-NEXT: NumberOfAuxEntries: 2
; SYM-NEXT: File Auxiliary Entry {
diff --git a/llvm/test/DebugInfo/XCOFF/empty.ll b/llvm/test/DebugInfo/XCOFF/empty.ll
index c1393907169fc..a9e2c2a3e2a2e 100644
--- a/llvm/test/DebugInfo/XCOFF/empty.ll
+++ b/llvm/test/DebugInfo/XCOFF/empty.ll
@@ -36,6 +36,7 @@ entry:
!12 = !DILocation(line: 3, column: 3, scope: !8)
; ASM32: .file "1.c"
+; ASM32-NEXT: .machine "pwr7"
; ASM32-NEXT: .csect ..text..[PR],5
; ASM32-NEXT: .rename ..text..[PR],""
; ASM32-NEXT: .globl main[DS] # -- Begin function main
@@ -238,6 +239,7 @@ entry:
; ASM32-NEXT: L..debug_line_end0:
; ASM64: .file "1.c"
+; ASM64-NEXT: .machine "pwr7"
; ASM64-NEXT: .csect ..text..[PR],5
; ASM64-NEXT: .rename ..text..[PR],""
; ASM64-NEXT: .globl main[DS] # -- Begin function main
diff --git a/llvm/test/DebugInfo/XCOFF/explicit-section.ll b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
index ed2ffb709168e..6dcfcd2dacd0d 100644
--- a/llvm/test/DebugInfo/XCOFF/explicit-section.ll
+++ b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
@@ -43,6 +43,7 @@ entry:
!16 = !DILocation(line: 3, column: 3, scope: !14)
; CHECK: .file "2.c"
+; CHECK-NEXT: .machine "pwr7"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
; CHECK-NEXT: .globl bar[DS] # -- Begin function bar
diff --git a/llvm/test/DebugInfo/XCOFF/function-sections.ll b/llvm/test/DebugInfo/XCOFF/function-sections.ll
index c899089102c64..1276e9533132b 100644
--- a/llvm/test/DebugInfo/XCOFF/function-sections.ll
+++ b/llvm/test/DebugInfo/XCOFF/function-sections.ll
@@ -38,6 +38,7 @@ entry:
!14 = !DILocation(line: 8, column: 3, scope: !13)
; CHECK: .file "1.c"
+; CHECK-NEXT: .machine "pwr7"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
; CHECK-NEXT: .csect .foo[PR],5
diff --git a/llvm/test/tools/llvm-readobj/XCOFF/symbols-invalid.test b/llvm/test/tools/llvm-readobj/XCOFF/symbols-invalid.test
index 3db8803149242..756417834b424 100644
--- a/llvm/test/tools/llvm-readobj/XCOFF/symbols-invalid.test
+++ b/llvm/test/tools/llvm-readobj/XCOFF/symbols-invalid.test
@@ -41,7 +41,7 @@ Symbols:
# CASE5-NEXT: Value (SymbolTableIndex): 0x0
# CASE5-NEXT: Section: N_UNDEF
# CASE5-NEXT: Source Language ID: TB_C (0x0)
-# CASE5-NEXT: CPU Version ID: 0x0
+# CASE5-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# CASE5-NEXT: StorageClass: C_FILE (0x67)
# CASE5-NEXT: NumberOfAuxEntries: 1
# CASE5-NEXT: !Unexpected raw auxiliary entry data:
diff --git a/llvm/test/tools/llvm-readobj/XCOFF/symbols.test b/llvm/test/tools/llvm-readobj/XCOFF/symbols.test
index 89439a3d0f02d..71347a85f1ba5 100644
--- a/llvm/test/tools/llvm-readobj/XCOFF/symbols.test
+++ b/llvm/test/tools/llvm-readobj/XCOFF/symbols.test
@@ -170,7 +170,7 @@ Symbols:
# SYMBOL32-NEXT: Value (SymbolTableIndex): 0x0
# SYMBOL32-NEXT: Section: N_DEBUG
# SYMBOL32-NEXT: Source Language ID: TB_C (0x0)
-# SYMBOL32-NEXT: CPU Version ID: 0x0
+# SYMBOL32-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# SYMBOL32-NEXT: StorageClass: C_FILE (0x67)
# SYMBOL32-NEXT: NumberOfAuxEntries: 3
# SYMBOL32-NEXT: File Auxiliary Entry {
diff --git a/llvm/test/tools/llvm-readobj/XCOFF/symbols64.test b/llvm/test/tools/llvm-readobj/XCOFF/symbols64.test
index 591c131063fe3..2b9edb3829af8 100644
--- a/llvm/test/tools/llvm-readobj/XCOFF/symbols64.test
+++ b/llvm/test/tools/llvm-readobj/XCOFF/symbols64.test
@@ -145,7 +145,7 @@ Symbols:
# SYMBOL64-NEXT: Value (SymbolTableIndex): 0x0
# SYMBOL64-NEXT: Section: N_DEBUG
# SYMBOL64-NEXT: Source Language ID: TB_C (0x0)
-# SYMBOL64-NEXT: CPU Version ID: 0x0
+# SYMBOL64-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# SYMBOL64-NEXT: StorageClass: C_FILE (0x67)
# SYMBOL64-NEXT: NumberOfAuxEntries: 3
# SYMBOL64-NEXT: File Auxiliary Entry {
diff --git a/llvm/test/tools/yaml2obj/XCOFF/aux-symbols.yaml b/llvm/test/tools/yaml2obj/XCOFF/aux-symbols.yaml
index 04c774dcc3ae2..ab9478de8f215 100644
--- a/llvm/test/tools/yaml2obj/XCOFF/aux-symbols.yaml
+++ b/llvm/test/tools/yaml2obj/XCOFF/aux-symbols.yaml
@@ -69,7 +69,7 @@
# DEFAULT32-NEXT: Value (SymbolTableIndex): 0x0
# DEFAULT32-NEXT: Section: N_UNDEF
# DEFAULT32-NEXT: Source Language ID: TB_C (0x0)
-# DEFAULT32-NEXT: CPU Version ID: 0x0
+# DEFAULT32-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# DEFAULT32-NEXT: StorageClass: C_FILE (0x67)
# DEFAULT32-NEXT: NumberOfAuxEntries: 1
# DEFAULT32-NEXT: File Auxiliary Entry {
@@ -213,7 +213,7 @@ Symbols:
# NON-DEFAULT32-NEXT: Value (SymbolTableIndex): 0x0
# NON-DEFAULT32-NEXT: Section: N_UNDEF
# NON-DEFAULT32-NEXT: Source Language ID: TB_C (0x0)
-# NON-DEFAULT32-NEXT: CPU Version ID: 0x0
+# NON-DEFAULT32-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# NON-DEFAULT32-NEXT: StorageClass: C_FILE (0x67)
# NON-DEFAULT32-NEXT: NumberOfAuxEntries: 1
# NON-DEFAULT32-NEXT: File Auxiliary Entry {
@@ -296,7 +296,7 @@ Symbols:
# DEFAULT64-NEXT: Value (SymbolTableIndex): 0x0
# DEFAULT64-NEXT: Section: N_UNDEF
# DEFAULT64-NEXT: Source Language ID: TB_C (0x0)
-# DEFAULT64-NEXT: CPU Version ID: 0x0
+# DEFAULT64-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# DEFAULT64-NEXT: StorageClass: C_FILE (0x67)
# DEFAULT64-NEXT: NumberOfAuxEntries: 1
# DEFAULT64-NEXT: File Auxiliary Entry {
@@ -426,7 +426,7 @@ Symbols:
# NON-DEFAULT64-NEXT: Value (SymbolTableIndex): 0x0
# NON-DEFAULT64-NEXT: Section: N_UNDEF
# NON-DEFAULT64-NEXT: Source Language ID: TB_C (0x0)
-# NON-DEFAULT64-NEXT: CPU Version ID: 0x0
+# NON-DEFAULT64-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# NON-DEFAULT64-NEXT: StorageClass: C_FILE (0x67)
# NON-DEFAULT64-NEXT: NumberOfAuxEntries: 1
# NON-DEFAULT64-NEXT: File Auxiliary Entry {
@@ -466,7 +466,7 @@ Symbols:
# FILENAME-NEXT: Value (SymbolTableIndex): 0x0
# FILENAME-NEXT: Section: N_UNDEF
# FILENAME-NEXT: Source Language ID: TB_C (0x0)
-# FILENAME-NEXT: CPU Version ID: 0x0
+# FILENAME-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# FILENAME-NEXT: StorageClass: C_FILE (0x67)
# FILENAME-NEXT: NumberOfAuxEntries: 1
# FILENAME-NEXT: File Auxiliary Entry {
@@ -554,7 +554,7 @@ Symbols:
# AUXNUM-NEXT: Value (SymbolTableIndex): 0x0
# AUXNUM-NEXT: Section: N_UNDEF
# AUXNUM-NEXT: Source Language ID: TB_C (0x0)
-# AUXNUM-NEXT: CPU Version ID: 0x0
+# AUXNUM-NEXT: CPU Version ID: TCPU_INVALID (0x0)
# AUXNUM-NEXT: StorageClass: C_FILE (0x67)
# AUXNUM-NEXT: NumberOfAuxEntries: 2
# AUXNUM-NEXT: File Auxiliary Entry {
diff --git a/llvm/tools/llvm-readobj/XCOFFDumper.cpp b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
index 46b510cfb06a3..9bbeaaeab55e3 100644
--- a/llvm/tools/llvm-readobj/XCOFFDumper.cpp
+++ b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
@@ -723,7 +723,20 @@ const EnumEntry<XCOFF::CFileLangId> CFileLangIdClass[] = {
const EnumEntry<XCOFF::CFileCpuId> CFileCpuIdClass[] = {
#define ECase(X) \
{ #X, XCOFF::X }
- ECase(TCPU_PPC64), ECase(TCPU_COM), ECase(TCPU_970)
+ ECase(TCPU_INVALID),
+ ECase(TCPU_PPC),
+ ECase(TCPU_PPC64),
+ ECase(TCPU_COM),
+ ECase(TCPU_PWR),
+ ECase(TCPU_970),
+ ECase(TCPU_PWR5),
+ ECase(TCPU_PWR6),
+ ECase(TCPU_PWR5X),
+ ECase(TCPU_PWR6E),
+ ECase(TCPU_PWR7),
+ ECase(TCPU_PWR8),
+ ECase(TCPU_PWR9),
+ ECase(TCPU_PWR10)
#undef ECase
};
>From 42f32124a88258f583f9f5f886ef9460ca50e869 Mon Sep 17 00:00:00 2001
From: esmeyi <esme.yi at ibm.com>
Date: Fri, 14 Jun 2024 03:16:30 -0400
Subject: [PATCH 2/7] Format.
---
llvm/tools/llvm-readobj/XCOFFDumper.cpp | 18 ++++--------------
1 file changed, 4 insertions(+), 14 deletions(-)
diff --git a/llvm/tools/llvm-readobj/XCOFFDumper.cpp b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
index 9bbeaaeab55e3..668564545028c 100644
--- a/llvm/tools/llvm-readobj/XCOFFDumper.cpp
+++ b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
@@ -723,20 +723,10 @@ const EnumEntry<XCOFF::CFileLangId> CFileLangIdClass[] = {
const EnumEntry<XCOFF::CFileCpuId> CFileCpuIdClass[] = {
#define ECase(X) \
{ #X, XCOFF::X }
- ECase(TCPU_INVALID),
- ECase(TCPU_PPC),
- ECase(TCPU_PPC64),
- ECase(TCPU_COM),
- ECase(TCPU_PWR),
- ECase(TCPU_970),
- ECase(TCPU_PWR5),
- ECase(TCPU_PWR6),
- ECase(TCPU_PWR5X),
- ECase(TCPU_PWR6E),
- ECase(TCPU_PWR7),
- ECase(TCPU_PWR8),
- ECase(TCPU_PWR9),
- ECase(TCPU_PWR10)
+ ECase(TCPU_INVALID), ECase(TCPU_PPC), ECase(TCPU_PPC64), ECase(TCPU_COM),
+ ECase(TCPU_PWR), ECase(TCPU_970), ECase(TCPU_PWR5), ECase(TCPU_PWR6),
+ ECase(TCPU_PWR5X), ECase(TCPU_PWR6E), ECase(TCPU_PWR7), ECase(TCPU_PWR8),
+ ECase(TCPU_PWR9), ECase(TCPU_PWR10)
#undef ECase
};
>From db40284f3d3ebedbb4eaef84875f1edb7a546831 Mon Sep 17 00:00:00 2001
From: esmeyi <esme.yi at ibm.com>
Date: Fri, 21 Jun 2024 03:17:59 -0400
Subject: [PATCH 3/7] Address comments.
---
llvm/include/llvm/BinaryFormat/XCOFF.h | 10 +++++++
llvm/include/llvm/MC/MCAssembler.h | 4 +--
llvm/lib/BinaryFormat/XCOFF.cpp | 29 +++++++++++++------
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 21 +++++++++++---
llvm/lib/MC/MCObjectStreamer.cpp | 2 +-
llvm/test/CodeGen/PowerPC/aix-cpu-version.ll | 17 +++++++++++
llvm/test/CodeGen/PowerPC/aix-filename-c.ll | 6 ++--
llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-filename-f.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll | 2 +-
.../PowerPC/aix-tls-xcoff-reloc-large.ll | 2 +-
.../PowerPC/aix-tls-xcoff-variables.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 6 ++--
llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 2 +-
llvm/test/DebugInfo/XCOFF/empty.ll | 4 +--
llvm/test/DebugInfo/XCOFF/explicit-section.ll | 2 +-
.../test/DebugInfo/XCOFF/function-sections.ll | 2 +-
llvm/tools/llvm-readobj/XCOFFDumper.cpp | 6 ++--
18 files changed, 87 insertions(+), 34 deletions(-)
create mode 100644 llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
diff --git a/llvm/include/llvm/BinaryFormat/XCOFF.h b/llvm/include/llvm/BinaryFormat/XCOFF.h
index 5e8d30b991f45..9c7464fbc19de 100644
--- a/llvm/include/llvm/BinaryFormat/XCOFF.h
+++ b/llvm/include/llvm/BinaryFormat/XCOFF.h
@@ -339,15 +339,25 @@ enum CFileCpuId : uint8_t {
TCPU_PPC64 = 2, ///< PowerPC common architecture 64-bit mode.
TCPU_COM = 3, ///< POWER and PowerPC architecture common.
TCPU_PWR = 4, ///< POWER common architecture objects.
+ TCPU_ANY = 5, ///< Mixture of any incompatable POWER
+ ///< and PowerPC architecture implementations.
+ TCPU_601 = 6, ///< 601 implementation of PowerPC architecture.
+ TCPU_603 = 7, ///< 603 implementation of PowerPC architecture.
+ TCPU_604 = 8, ///< 604 implementation of PowerPC architecture.
+ TCPU_PWR1 = 10, ///< RS1 implementation of POWER architecture.
+ TCPU_620 = 16, ///< 620 - PowerPC 64-bit architecture.
+ TCPU_A35 = 17, ///< A35 - PowerPC 64-bit architecture.
TCPU_PWR5 = 18, ///< PWR5 - PowerPC 64-bit architecture.
TCPU_970 = 19, ///< PPC970 - PowerPC 64-bit architecture.
TCPU_PWR6 = 20, ///< PWR6 - PowerPC 64-bit architecture.
+ TCPU_VEC = 21, ///< PowerPC 64-bit arch with Vector Extension.
TCPU_PWR5X = 22, ///< PWR5+ - PowerPC 64-bit architecture.
TCPU_PWR6E = 23, ///< PWR6E - PowerPC 64-bit architecture.
TCPU_PWR7 = 24, ///< PWR7 - PowerPC 64-bit architecture.
TCPU_PWR8 = 25, ///< PWR8 - PowerPC 64-bit architecture.
TCPU_PWR9 = 26, ///< PWR9 - PowerPC 64-bit architecture.
TCPU_PWR10 = 27, ///< PWR10 - PowerPC 64-bit architecture.
+ TCPU_PWRX = 224 ///< RS2 implementation of POWER architecture.
};
enum SymbolAuxType : uint8_t {
diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h
index 45f4befeb84d5..201b32d068207 100644
--- a/llvm/include/llvm/MC/MCAssembler.h
+++ b/llvm/include/llvm/MC/MCAssembler.h
@@ -136,7 +136,7 @@ class MCAssembler {
// Optional compiler version.
std::string CompilerVersion;
// PPC CPU type.
- StringRef CPU;
+ std::string CPU;
MCDwarfLineTableParams LTParams;
@@ -492,7 +492,7 @@ class MCAssembler {
}
StringRef getCompilerVersion() { return CompilerVersion; }
- void setCPU(StringRef TargetCPU) { CPU = TargetCPU; }
+ void setCPU(std::string TargetCPU) { CPU = std::move(TargetCPU); }
StringRef getCPU() { return CPU; }
/// Write the necessary bundle padding to \p OS.
diff --git a/llvm/lib/BinaryFormat/XCOFF.cpp b/llvm/lib/BinaryFormat/XCOFF.cpp
index f2e3b2e82f950..b4db893cfa1f5 100644
--- a/llvm/lib/BinaryFormat/XCOFF.cpp
+++ b/llvm/lib/BinaryFormat/XCOFF.cpp
@@ -110,15 +110,26 @@ StringRef XCOFF::getNameForTracebackTableLanguageId(
XCOFF::CFileCpuId XCOFF::getCpuID(StringRef CPU) {
return StringSwitch<XCOFF::CFileCpuId>(CPU)
- .Case("pwr4", XCOFF::TCPU_PWR)
- .Case("pwr5", XCOFF::TCPU_PWR5)
- .Case("pwr6", XCOFF::TCPU_PWR6)
- .Case("pwr5x", XCOFF::TCPU_PWR5X)
- .Case("pwr7", XCOFF::TCPU_PWR7)
- .Case("pwr8", XCOFF::TCPU_PWR8)
- .Case("pwr9", XCOFF::TCPU_PWR9)
- .Case("pwr10", XCOFF::TCPU_PWR10)
- .Default(XCOFF::TCPU_PWR7);
+ .Case("generic", XCOFF::TCPU_PWR7)
+ .Case("601", XCOFF::TCPU_601)
+ .Cases("602", "603", "603e", "603ev", XCOFF::TCPU_603)
+ .Cases("604", "604e", XCOFF::TCPU_604)
+ .Case("620", XCOFF::TCPU_620)
+ .Case("970", XCOFF::TCPU_970)
+ .Cases("pwr3", "power3", "pwr4", "power4", XCOFF::TCPU_PWR)
+ .Cases("pwr5", "power5", XCOFF::TCPU_PWR5)
+ .Cases("pwr5x", "power5x", XCOFF::TCPU_PWR5X)
+ .Cases("pwr6", "power6", XCOFF::TCPU_PWR6)
+ .Cases("pwr6x", "power6x", XCOFF::TCPU_PWR6E)
+ .Cases("pwr7", "power7", XCOFF::TCPU_PWR7)
+ .Cases("pwr8", "power8", XCOFF::TCPU_PWR8)
+ .Cases("pwr9", "power9", XCOFF::TCPU_PWR9)
+ .Cases("pwr10", "power10", XCOFF::TCPU_PWR10)
+ .Case("future", XCOFF::TCPU_PWRX)
+ .Cases("powerpc", "ppc", "ppc32", XCOFF::TCPU_PPC)
+ .Cases("powerpc64", "ppc64", "powerpc64le", "ppc64le", XCOFF::TCPU_PPC64)
+ .Case("any", XCOFF::TCPU_ANY)
+ .Default(XCOFF::TCPU_INVALID);
}
Expected<SmallString<32>> XCOFF::parseParmsType(uint32_t Value,
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index f9a7c37b70bf2..4f65dfb322842 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -514,14 +514,27 @@ bool AsmPrinter::doInitialization(Module &M) {
}
}
- // On AIX, emit bytes for llvm.commandline metadata after .file so that the
- // C_INFO symbol is preserved if any csect is kept by the linker.
if (TM.getTargetTriple().isOSBinFormatXCOFF()) {
// Emit .machine directive on AIX.
- StringRef TargetCPU =
- TM.getTargetCPU().empty() ? "pwr7" : TM.getTargetCPU();
+ StringRef TargetCPU;
+ // Walk through the target-cpu attribute of functions and use the newest
+ // level as the CPU of the module.
+ for (auto &F : M) {
+ StringRef FunCPU = TM.getSubtargetImpl(F)->getCPU();
+ if (XCOFF::getCpuID(FunCPU) > XCOFF::getCpuID(TargetCPU))
+ TargetCPU = FunCPU;
+ }
+ // If there is no "target-cpu" attr in functions, take the "-mcpu" value.
+ if (TargetCPU.empty()) {
+ if (!TM.getTargetCPU().empty())
+ TargetCPU = TM.getTargetCPU();
+ else
+ TargetCPU = "any";
+ }
OutStreamer->emitMachineDirective(TargetCPU);
+ // On AIX, emit bytes for llvm.commandline metadata after .file so that the
+ // C_INFO symbol is preserved if any csect is kept by the linker.
emitModuleCommandLines(M);
// Now we can generate section information.
OutStreamer->initSections(false, *TM.getMCSubtargetInfo());
diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp
index 80c1a8920177f..a801aab58b2d3 100644
--- a/llvm/lib/MC/MCObjectStreamer.cpp
+++ b/llvm/lib/MC/MCObjectStreamer.cpp
@@ -903,7 +903,7 @@ void MCObjectStreamer::emitFileDirective(StringRef Filename,
}
void MCObjectStreamer::emitMachineDirective(StringRef CPU) {
- getAssembler().setCPU(CPU);
+ getAssembler().setCPU(CPU.data());
}
void MCObjectStreamer::emitAddrsig() {
diff --git a/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
new file mode 100644
index 0000000000000..ee159c395ecc3
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
@@ -0,0 +1,17 @@
+; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+
+; CHECK: .file "1.c"
+; CHECK-NEXT: .machine "ppc64"
+; CHECK-NEXT: .csect ..text..[PR],5
+; CHECK-NEXT: .rename ..text..[PR],""
+
+source_filename = "1.c"
+
+define dso_local signext i32 @main() #0 {
+entry:
+ %retval = alloca i32, align 4
+ store i32 0, ptr %retval, align 4
+ ret i32 0
+}
+
+attributes #0 = {"target-cpu"="ppc64"}
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
index dd342c00176f3..96edad82137a8 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
@@ -7,7 +7,7 @@
source_filename = "1.c"
-; ASM: .file "1.c",,"LLVM version 19.0.0git"
+; ASM: .file "1.c",,"{{.*}}, LLVM version{{.*}}git"
; ASM-NEXT: .machine "pwr9"
; ASM-NEXT: .csect ..text..[PR],5
; ASM-NEXT: .rename ..text..[PR],""
@@ -28,7 +28,7 @@ source_filename = "1.c"
; OBJ32-NEXT: }
; OBJ32-NEXT: File Auxiliary Entry {
; OBJ32-NEXT: Index: 2
-; OBJ32-NEXT: Name: LLVM version 19.0.0git
+; OBJ32-NEXT: Name: {{.*}}, LLVM version{{.*}}git
; OBJ32-NEXT: Type: XFT_CV (0x2)
; OBJ32-NEXT: }
; OBJ32-NEXT: }
@@ -50,7 +50,7 @@ source_filename = "1.c"
; OBJ64-NEXT: }
; OBJ64-NEXT: File Auxiliary Entry {
; OBJ64-NEXT: Index: 2
-; OBJ64-NEXT: Name: LLVM version 19.0.0git
+; OBJ64-NEXT: Name: {{.*}}, LLVM version{{.*}}git
; OBJ64-NEXT: Type: XFT_CV (0x2)
; OBJ64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
; OBJ64-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
index 873619d20cd2c..b5e36471406b3 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
@@ -7,5 +7,5 @@ source_filename = "1.cpp"
; OBJ: Name: .file
; OBJ: Source Language ID: TB_CPLUSPLUS (0x9)
-; OBJ: CPU Version ID: TCPU_PWR7 (0x18)
+; OBJ: CPU Version ID: TCPU_ANY (0x5)
; OBJ: Name: 1.cpp
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
index 1167148d21a7f..d7be21c99f047 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll
@@ -7,5 +7,5 @@ source_filename = "1.f95"
; OBJ: Name: .file
; OBJ: Source Language ID: TB_Fortran (0x1)
-; OBJ: CPU Version ID: TCPU_PWR7 (0x18)
+; OBJ: CPU Version ID: TCPU_ANY (0x5)
; OBJ: Name: 1.f95
diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
index 50221acc2b3ad..ebd7c193a7f4c 100644
--- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
@@ -27,7 +27,7 @@ entry:
; CHECK-NEXT: }
; CHECK-NEXT: File Auxiliary Entry {
; CHECK-NEXT: Index: 2
-; CHECK-NEXT: Name: LLVM
+; CHECK-NEXT: Name: {{.*}}, LLVM version{{.*}}git
; CHECK-NEXT: Type: XFT_CV (0x2)
; CHECK-NEXT: }
; CHECK-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
index d943d9bd6cf10..caf9cc472b4bb 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
@@ -225,7 +225,7 @@ entry:
; SYM-NEXT: }
; SYM-NEXT: File Auxiliary Entry {
; SYM-NEXT: Index: 2
-; SYM-NEXT: Name: LLVM
+; SYM-NEXT: Name: {{.*}}, LLVM version{{.*}}git
; SYM-NEXT: Type: XFT_CV (0x2)
; SYM-NEXT: }
; SYM-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
index 3c84aa1225d2e..945dd56a2b67a 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
@@ -70,7 +70,7 @@
; SYMS-NEXT: Value (SymbolTableIndex): 0x0
; SYMS-NEXT: Section: N_DEBUG
; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYMS-NEXT: CPU Version ID: TCPU_PWR7 (0x18)
+; SYMS-NEXT: CPU Version ID: TCPU_ANY (0x5)
; SYMS-NEXT: StorageClass: C_FILE (0x67)
; SYMS-NEXT: NumberOfAuxEntries: 2
; SYMS: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
index e28751f10a12f..b8d1dd9663b73 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
@@ -46,7 +46,7 @@
; CHECK-NOT: .toc
; CHECK: .file
-; CHECK-NEXT: .machine "pwr7"
+; CHECK-NEXT: .machine "any"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK: .csect .data[RW],5
@@ -213,7 +213,7 @@
; SYMS-NEXT: Value (SymbolTableIndex): 0x0
; SYMS-NEXT: Section: N_DEBUG
; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYMS-NEXT: CPU Version ID: TCPU_PWR7 (0x18)
+; SYMS-NEXT: CPU Version ID: TCPU_ANY (0x5)
; SYMS-NEXT: StorageClass: C_FILE (0x67)
; SYMS-NEXT: NumberOfAuxEntries: 2
; SYMS-NEXT: File Auxiliary Entry {
@@ -224,7 +224,7 @@
; SYMS-NEXT: }
; SYMS-NEXT: File Auxiliary Entry {
; SYMS-NEXT: Index: 2
-; SYMS-NEXT: Name: LLVM
+; SYMS-NEXT: Name: {{.*}}, LLVM version{{.*}}git
; SYMS-NEXT: Type: XFT_CV (0x2)
; SYMS64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
; SYMS-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
index 541b3b1c19c05..c6ac18c010902 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -174,7 +174,7 @@ declare i32 @bar(i32)
; SYM-NEXT: }
; SYM-NEXT: File Auxiliary Entry {
; SYM-NEXT: Index: 2
-; SYM-NEXT: Name: LLVM
+; SYM-NEXT: Name: {{.*}}, LLVM version{{.*}}git
; SYM-NEXT: Type: XFT_CV (0x2)
; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
; SYM-NEXT: }
diff --git a/llvm/test/DebugInfo/XCOFF/empty.ll b/llvm/test/DebugInfo/XCOFF/empty.ll
index a9e2c2a3e2a2e..54f70b73e6209 100644
--- a/llvm/test/DebugInfo/XCOFF/empty.ll
+++ b/llvm/test/DebugInfo/XCOFF/empty.ll
@@ -36,7 +36,7 @@ entry:
!12 = !DILocation(line: 3, column: 3, scope: !8)
; ASM32: .file "1.c"
-; ASM32-NEXT: .machine "pwr7"
+; ASM32-NEXT: .machine "any"
; ASM32-NEXT: .csect ..text..[PR],5
; ASM32-NEXT: .rename ..text..[PR],""
; ASM32-NEXT: .globl main[DS] # -- Begin function main
@@ -239,7 +239,7 @@ entry:
; ASM32-NEXT: L..debug_line_end0:
; ASM64: .file "1.c"
-; ASM64-NEXT: .machine "pwr7"
+; ASM64-NEXT: .machine "any"
; ASM64-NEXT: .csect ..text..[PR],5
; ASM64-NEXT: .rename ..text..[PR],""
; ASM64-NEXT: .globl main[DS] # -- Begin function main
diff --git a/llvm/test/DebugInfo/XCOFF/explicit-section.ll b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
index 6dcfcd2dacd0d..365cb70433e04 100644
--- a/llvm/test/DebugInfo/XCOFF/explicit-section.ll
+++ b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
@@ -43,7 +43,7 @@ entry:
!16 = !DILocation(line: 3, column: 3, scope: !14)
; CHECK: .file "2.c"
-; CHECK-NEXT: .machine "pwr7"
+; CHECK-NEXT: .machine "any"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
; CHECK-NEXT: .globl bar[DS] # -- Begin function bar
diff --git a/llvm/test/DebugInfo/XCOFF/function-sections.ll b/llvm/test/DebugInfo/XCOFF/function-sections.ll
index 1276e9533132b..b8709eed04ea9 100644
--- a/llvm/test/DebugInfo/XCOFF/function-sections.ll
+++ b/llvm/test/DebugInfo/XCOFF/function-sections.ll
@@ -38,7 +38,7 @@ entry:
!14 = !DILocation(line: 8, column: 3, scope: !13)
; CHECK: .file "1.c"
-; CHECK-NEXT: .machine "pwr7"
+; CHECK-NEXT: .machine "any"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
; CHECK-NEXT: .csect .foo[PR],5
diff --git a/llvm/tools/llvm-readobj/XCOFFDumper.cpp b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
index 668564545028c..5af29dc0134c7 100644
--- a/llvm/tools/llvm-readobj/XCOFFDumper.cpp
+++ b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
@@ -724,9 +724,11 @@ const EnumEntry<XCOFF::CFileCpuId> CFileCpuIdClass[] = {
#define ECase(X) \
{ #X, XCOFF::X }
ECase(TCPU_INVALID), ECase(TCPU_PPC), ECase(TCPU_PPC64), ECase(TCPU_COM),
- ECase(TCPU_PWR), ECase(TCPU_970), ECase(TCPU_PWR5), ECase(TCPU_PWR6),
+ ECase(TCPU_PWR), ECase(TCPU_ANY), ECase(TCPU_601), ECase(TCPU_603),
+ ECase(TCPU_604), ECase(TCPU_620), ECase(TCPU_A35), ECase(TCPU_970),
+ ECase(TCPU_PWR1), ECase(TCPU_PWR5), ECase(TCPU_PWR6), ECase(TCPU_VEC),
ECase(TCPU_PWR5X), ECase(TCPU_PWR6E), ECase(TCPU_PWR7), ECase(TCPU_PWR8),
- ECase(TCPU_PWR9), ECase(TCPU_PWR10)
+ ECase(TCPU_PWR9), ECase(TCPU_PWR10), ECase(TCPU_PWRX)
#undef ECase
};
>From 62ef96ac2df61aff6603d42ea14cc967d1c9919d Mon Sep 17 00:00:00 2001
From: Esme <esme.yi at ibm.com>
Date: Fri, 21 Jun 2024 16:21:33 +0800
Subject: [PATCH 4/7] Update llvm/include/llvm/MC/MCAssembler.h
Co-authored-by: Kai Luo <gluokai at gmail.com>
---
llvm/include/llvm/MC/MCAssembler.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h
index 201b32d068207..21359d9eb9704 100644
--- a/llvm/include/llvm/MC/MCAssembler.h
+++ b/llvm/include/llvm/MC/MCAssembler.h
@@ -493,7 +493,7 @@ class MCAssembler {
StringRef getCompilerVersion() { return CompilerVersion; }
void setCPU(std::string TargetCPU) { CPU = std::move(TargetCPU); }
- StringRef getCPU() { return CPU; }
+ StringRef getCPU() const { return CPU; }
/// Write the necessary bundle padding to \p OS.
/// Expects a fragment \p F containing instructions and its size \p FSize.
>From c50100b86bfc0fab10331f1bc81ba33a430d5c81 Mon Sep 17 00:00:00 2001
From: esmeyi <esme.yi at ibm.com>
Date: Tue, 25 Jun 2024 01:48:57 -0400
Subject: [PATCH 5/7] Emit valid machine directive for AIX system as.
---
llvm/include/llvm/BinaryFormat/XCOFF.h | 1 +
llvm/lib/BinaryFormat/XCOFF.cpp | 58 +++++++++++++++----
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 19 +++---
llvm/test/CodeGen/PowerPC/aix-cpu-version.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-filename-c.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 2 +-
llvm/test/DebugInfo/XCOFF/empty.ll | 4 +-
llvm/test/DebugInfo/XCOFF/explicit-section.ll | 2 +-
.../test/DebugInfo/XCOFF/function-sections.ll | 2 +-
9 files changed, 64 insertions(+), 28 deletions(-)
diff --git a/llvm/include/llvm/BinaryFormat/XCOFF.h b/llvm/include/llvm/BinaryFormat/XCOFF.h
index 9c7464fbc19de..00ca4e1699b7e 100644
--- a/llvm/include/llvm/BinaryFormat/XCOFF.h
+++ b/llvm/include/llvm/BinaryFormat/XCOFF.h
@@ -371,6 +371,7 @@ enum SymbolAuxType : uint8_t {
StringRef getMappingClassString(XCOFF::StorageMappingClass SMC);
StringRef getRelocationTypeString(XCOFF::RelocationType Type);
+StringRef getTCPUString(XCOFF::CFileCpuId TCPU);
Expected<SmallString<32>> parseParmsType(uint32_t Value, unsigned FixedParmsNum,
unsigned FloatingParmsNum);
Expected<SmallString<32>> parseParmsTypeWithVecInfo(uint32_t Value,
diff --git a/llvm/lib/BinaryFormat/XCOFF.cpp b/llvm/lib/BinaryFormat/XCOFF.cpp
index b4db893cfa1f5..9054791c30b5d 100644
--- a/llvm/lib/BinaryFormat/XCOFF.cpp
+++ b/llvm/lib/BinaryFormat/XCOFF.cpp
@@ -116,22 +116,56 @@ XCOFF::CFileCpuId XCOFF::getCpuID(StringRef CPU) {
.Cases("604", "604e", XCOFF::TCPU_604)
.Case("620", XCOFF::TCPU_620)
.Case("970", XCOFF::TCPU_970)
- .Cases("pwr3", "power3", "pwr4", "power4", XCOFF::TCPU_PWR)
- .Cases("pwr5", "power5", XCOFF::TCPU_PWR5)
- .Cases("pwr5x", "power5x", XCOFF::TCPU_PWR5X)
- .Cases("pwr6", "power6", XCOFF::TCPU_PWR6)
- .Cases("pwr6x", "power6x", XCOFF::TCPU_PWR6E)
- .Cases("pwr7", "power7", XCOFF::TCPU_PWR7)
- .Cases("pwr8", "power8", XCOFF::TCPU_PWR8)
- .Cases("pwr9", "power9", XCOFF::TCPU_PWR9)
- .Cases("pwr10", "power10", XCOFF::TCPU_PWR10)
+ .Cases("pwr3", "power3", "pwr4", "power4", "PWR", XCOFF::TCPU_PWR)
+ .Cases("pwr5", "power5", "PWR5", XCOFF::TCPU_PWR5)
+ .Cases("pwr5x", "power5x", "PWR5X", XCOFF::TCPU_PWR5X)
+ .Cases("pwr6", "power6", "PWR6", XCOFF::TCPU_PWR6)
+ .Cases("pwr6x", "power6x", "PWR6E", XCOFF::TCPU_PWR6E)
+ .Cases("pwr7", "power7", "PWR7", XCOFF::TCPU_PWR7)
+ .Cases("pwr8", "power8", "PWR8", XCOFF::TCPU_PWR8)
+ .Cases("pwr9", "power9", "PWR9", XCOFF::TCPU_PWR9)
+ .Cases("pwr10", "power10", "PWR10", XCOFF::TCPU_PWR10)
.Case("future", XCOFF::TCPU_PWRX)
- .Cases("powerpc", "ppc", "ppc32", XCOFF::TCPU_PPC)
- .Cases("powerpc64", "ppc64", "powerpc64le", "ppc64le", XCOFF::TCPU_PPC64)
- .Case("any", XCOFF::TCPU_ANY)
+ .Cases("powerpc", "ppc", "ppc32", "PPC", XCOFF::TCPU_PPC)
+ .Cases("powerpc64", "ppc64", "powerpc64le", "ppc64le", "PPC64",
+ XCOFF::TCPU_PPC64)
+ .Cases("any", "ANY", XCOFF::TCPU_ANY)
.Default(XCOFF::TCPU_INVALID);
}
+#define TCPU_CASE(A) \
+ case XCOFF::TCPU_##A: \
+ return #A;
+StringRef XCOFF::getTCPUString(XCOFF::CFileCpuId TCPU) {
+ switch (TCPU) {
+ TCPU_CASE(INVALID)
+ TCPU_CASE(PPC)
+ TCPU_CASE(PPC64)
+ TCPU_CASE(COM)
+ TCPU_CASE(PWR)
+ TCPU_CASE(ANY)
+ TCPU_CASE(601)
+ TCPU_CASE(603)
+ TCPU_CASE(604)
+ TCPU_CASE(620)
+ TCPU_CASE(A35)
+ TCPU_CASE(PWR1)
+ TCPU_CASE(PWR5)
+ TCPU_CASE(970)
+ TCPU_CASE(PWR6)
+ TCPU_CASE(VEC)
+ TCPU_CASE(PWR5X)
+ TCPU_CASE(PWR6E)
+ TCPU_CASE(PWR7)
+ TCPU_CASE(PWR8)
+ TCPU_CASE(PWR9)
+ TCPU_CASE(PWR10)
+ TCPU_CASE(PWRX)
+ }
+ return "INVALID";
+}
+#undef TCPU_CASE
+
Expected<SmallString<32>> XCOFF::parseParmsType(uint32_t Value,
unsigned FixedParmsNum,
unsigned FloatingParmsNum) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 4f65dfb322842..5b4eb6bda3b19 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -516,22 +516,23 @@ bool AsmPrinter::doInitialization(Module &M) {
if (TM.getTargetTriple().isOSBinFormatXCOFF()) {
// Emit .machine directive on AIX.
- StringRef TargetCPU;
- // Walk through the target-cpu attribute of functions and use the newest
+ XCOFF::CFileCpuId TargetCpuId = XCOFF::TCPU_INVALID;
+ // Walk through the "target-cpu" attribute of functions and use the newest
// level as the CPU of the module.
for (auto &F : M) {
- StringRef FunCPU = TM.getSubtargetImpl(F)->getCPU();
- if (XCOFF::getCpuID(FunCPU) > XCOFF::getCpuID(TargetCPU))
- TargetCPU = FunCPU;
+ XCOFF::CFileCpuId FunCpuId =
+ XCOFF::getCpuID(TM.getSubtargetImpl(F)->getCPU());
+ if (FunCpuId > TargetCpuId)
+ TargetCpuId = FunCpuId;
}
// If there is no "target-cpu" attr in functions, take the "-mcpu" value.
- if (TargetCPU.empty()) {
+ if (!TargetCpuId) {
if (!TM.getTargetCPU().empty())
- TargetCPU = TM.getTargetCPU();
+ TargetCpuId = XCOFF::getCpuID(TM.getTargetCPU());
else
- TargetCPU = "any";
+ TargetCpuId = XCOFF::TCPU_ANY;
}
- OutStreamer->emitMachineDirective(TargetCPU);
+ OutStreamer->emitMachineDirective(XCOFF::getTCPUString(TargetCpuId));
// On AIX, emit bytes for llvm.commandline metadata after .file so that the
// C_INFO symbol is preserved if any csect is kept by the linker.
diff --git a/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
index ee159c395ecc3..bf1e53ef13f19 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
; CHECK: .file "1.c"
-; CHECK-NEXT: .machine "ppc64"
+; CHECK-NEXT: .machine "PPC64"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
index 96edad82137a8..ac5e03c158ca3 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
@@ -8,7 +8,7 @@
source_filename = "1.c"
; ASM: .file "1.c",,"{{.*}}, LLVM version{{.*}}git"
-; ASM-NEXT: .machine "pwr9"
+; ASM-NEXT: .machine "PWR9"
; ASM-NEXT: .csect ..text..[PR],5
; ASM-NEXT: .rename ..text..[PR],""
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
index b8d1dd9663b73..d9cd60a4a0540 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
@@ -46,7 +46,7 @@
; CHECK-NOT: .toc
; CHECK: .file
-; CHECK-NEXT: .machine "any"
+; CHECK-NEXT: .machine "ANY"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK: .csect .data[RW],5
diff --git a/llvm/test/DebugInfo/XCOFF/empty.ll b/llvm/test/DebugInfo/XCOFF/empty.ll
index 54f70b73e6209..f4c1f6e000583 100644
--- a/llvm/test/DebugInfo/XCOFF/empty.ll
+++ b/llvm/test/DebugInfo/XCOFF/empty.ll
@@ -36,7 +36,7 @@ entry:
!12 = !DILocation(line: 3, column: 3, scope: !8)
; ASM32: .file "1.c"
-; ASM32-NEXT: .machine "any"
+; ASM32-NEXT: .machine "ANY"
; ASM32-NEXT: .csect ..text..[PR],5
; ASM32-NEXT: .rename ..text..[PR],""
; ASM32-NEXT: .globl main[DS] # -- Begin function main
@@ -239,7 +239,7 @@ entry:
; ASM32-NEXT: L..debug_line_end0:
; ASM64: .file "1.c"
-; ASM64-NEXT: .machine "any"
+; ASM64-NEXT: .machine "ANY"
; ASM64-NEXT: .csect ..text..[PR],5
; ASM64-NEXT: .rename ..text..[PR],""
; ASM64-NEXT: .globl main[DS] # -- Begin function main
diff --git a/llvm/test/DebugInfo/XCOFF/explicit-section.ll b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
index 365cb70433e04..7fd1066cb764b 100644
--- a/llvm/test/DebugInfo/XCOFF/explicit-section.ll
+++ b/llvm/test/DebugInfo/XCOFF/explicit-section.ll
@@ -43,7 +43,7 @@ entry:
!16 = !DILocation(line: 3, column: 3, scope: !14)
; CHECK: .file "2.c"
-; CHECK-NEXT: .machine "any"
+; CHECK-NEXT: .machine "ANY"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
; CHECK-NEXT: .globl bar[DS] # -- Begin function bar
diff --git a/llvm/test/DebugInfo/XCOFF/function-sections.ll b/llvm/test/DebugInfo/XCOFF/function-sections.ll
index b8709eed04ea9..77824d02b4ec9 100644
--- a/llvm/test/DebugInfo/XCOFF/function-sections.ll
+++ b/llvm/test/DebugInfo/XCOFF/function-sections.ll
@@ -38,7 +38,7 @@ entry:
!14 = !DILocation(line: 8, column: 3, scope: !13)
; CHECK: .file "1.c"
-; CHECK-NEXT: .machine "any"
+; CHECK-NEXT: .machine "ANY"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
; CHECK-NEXT: .csect .foo[PR],5
>From 3fc8a7caeac4d1c3e33d968c7536e6185f1efe17 Mon Sep 17 00:00:00 2001
From: esmeyi <esme.yi at ibm.com>
Date: Tue, 25 Jun 2024 04:24:11 -0400
Subject: [PATCH 6/7] Adjust the mapping of cpu values between mcpu, assembler
and xcoff.
---
llvm/include/llvm/BinaryFormat/XCOFF.h | 4 +---
llvm/lib/BinaryFormat/XCOFF.cpp | 13 +++++--------
llvm/test/CodeGen/PowerPC/aix-cpu-version.ll | 4 ++--
llvm/test/CodeGen/PowerPC/aix-extern-weak.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-extern.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll | 2 +-
.../CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-weak.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 2 +-
llvm/tools/llvm-readobj/XCOFFDumper.cpp | 12 ++++++------
11 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/llvm/include/llvm/BinaryFormat/XCOFF.h b/llvm/include/llvm/BinaryFormat/XCOFF.h
index 00ca4e1699b7e..687bfcdc84d1f 100644
--- a/llvm/include/llvm/BinaryFormat/XCOFF.h
+++ b/llvm/include/llvm/BinaryFormat/XCOFF.h
@@ -344,14 +344,12 @@ enum CFileCpuId : uint8_t {
TCPU_601 = 6, ///< 601 implementation of PowerPC architecture.
TCPU_603 = 7, ///< 603 implementation of PowerPC architecture.
TCPU_604 = 8, ///< 604 implementation of PowerPC architecture.
- TCPU_PWR1 = 10, ///< RS1 implementation of POWER architecture.
TCPU_620 = 16, ///< 620 - PowerPC 64-bit architecture.
TCPU_A35 = 17, ///< A35 - PowerPC 64-bit architecture.
TCPU_PWR5 = 18, ///< PWR5 - PowerPC 64-bit architecture.
TCPU_970 = 19, ///< PPC970 - PowerPC 64-bit architecture.
TCPU_PWR6 = 20, ///< PWR6 - PowerPC 64-bit architecture.
- TCPU_VEC = 21, ///< PowerPC 64-bit arch with Vector Extension.
- TCPU_PWR5X = 22, ///< PWR5+ - PowerPC 64-bit architecture.
+ TCPU_PWR5X = 22, ///< PWR5X - PowerPC 64-bit architecture.
TCPU_PWR6E = 23, ///< PWR6E - PowerPC 64-bit architecture.
TCPU_PWR7 = 24, ///< PWR7 - PowerPC 64-bit architecture.
TCPU_PWR8 = 25, ///< PWR8 - PowerPC 64-bit architecture.
diff --git a/llvm/lib/BinaryFormat/XCOFF.cpp b/llvm/lib/BinaryFormat/XCOFF.cpp
index 9054791c30b5d..79d5233af7605 100644
--- a/llvm/lib/BinaryFormat/XCOFF.cpp
+++ b/llvm/lib/BinaryFormat/XCOFF.cpp
@@ -116,7 +116,7 @@ XCOFF::CFileCpuId XCOFF::getCpuID(StringRef CPU) {
.Cases("604", "604e", XCOFF::TCPU_604)
.Case("620", XCOFF::TCPU_620)
.Case("970", XCOFF::TCPU_970)
- .Cases("pwr3", "power3", "pwr4", "power4", "PWR", XCOFF::TCPU_PWR)
+ .Cases("pwr3", "power3", "pwr4", "power4", "COM", XCOFF::TCPU_COM)
.Cases("pwr5", "power5", "PWR5", XCOFF::TCPU_PWR5)
.Cases("pwr5x", "power5x", "PWR5X", XCOFF::TCPU_PWR5X)
.Cases("pwr6", "power6", "PWR6", XCOFF::TCPU_PWR6)
@@ -125,16 +125,15 @@ XCOFF::CFileCpuId XCOFF::getCpuID(StringRef CPU) {
.Cases("pwr8", "power8", "PWR8", XCOFF::TCPU_PWR8)
.Cases("pwr9", "power9", "PWR9", XCOFF::TCPU_PWR9)
.Cases("pwr10", "power10", "PWR10", XCOFF::TCPU_PWR10)
- .Case("future", XCOFF::TCPU_PWRX)
- .Cases("powerpc", "ppc", "ppc32", "PPC", XCOFF::TCPU_PPC)
+ .Cases("powerpc", "ppc", "ppc32", XCOFF::TCPU_ANY)
.Cases("powerpc64", "ppc64", "powerpc64le", "ppc64le", "PPC64",
- XCOFF::TCPU_PPC64)
- .Cases("any", "ANY", XCOFF::TCPU_ANY)
+ XCOFF::TCPU_ANY)
+ .Cases("any", "ANY", "future", XCOFF::TCPU_ANY)
.Default(XCOFF::TCPU_INVALID);
}
#define TCPU_CASE(A) \
- case XCOFF::TCPU_##A: \
+ case XCOFF::TCPU_##A: \
return #A;
StringRef XCOFF::getTCPUString(XCOFF::CFileCpuId TCPU) {
switch (TCPU) {
@@ -149,11 +148,9 @@ StringRef XCOFF::getTCPUString(XCOFF::CFileCpuId TCPU) {
TCPU_CASE(604)
TCPU_CASE(620)
TCPU_CASE(A35)
- TCPU_CASE(PWR1)
TCPU_CASE(PWR5)
TCPU_CASE(970)
TCPU_CASE(PWR6)
- TCPU_CASE(VEC)
TCPU_CASE(PWR5X)
TCPU_CASE(PWR6E)
TCPU_CASE(PWR7)
diff --git a/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
index bf1e53ef13f19..f9ef6c642b0c1 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cpu-version.ll
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
; CHECK: .file "1.c"
-; CHECK-NEXT: .machine "PPC64"
+; CHECK-NEXT: .machine "PWR8"
; CHECK-NEXT: .csect ..text..[PR],5
; CHECK-NEXT: .rename ..text..[PR],""
@@ -14,4 +14,4 @@ entry:
ret i32 0
}
-attributes #0 = {"target-cpu"="ppc64"}
+attributes #0 = {"target-cpu"="pwr8"}
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
index ab62cd95ae2a4..26846d80d6647 100644
--- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -69,7 +69,7 @@ declare extern_weak void @foo_ext_weak(ptr)
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll
index 825e30242ed50..fc2b9effdf30d 100644
--- a/llvm/test/CodeGen/PowerPC/aix-extern.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll
@@ -92,7 +92,7 @@ declare i32 @bar_extern(ptr)
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
index dc849c4f8933f..e2a3febd6c976 100644
--- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
@@ -44,7 +44,7 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg)
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
index caf9cc472b4bb..a35299a6fbd8b 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
@@ -215,7 +215,7 @@ entry:
; SYM-NEXT: Value (SymbolTableIndex): 0x0
; SYM-NEXT: Section: N_DEBUG
; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
+; SYM-NEXT: CPU Version ID: TCPU_COM (0x3)
; SYM-NEXT: StorageClass: C_FILE (0x67)
; SYM-NEXT: NumberOfAuxEntries: 2
; SYM-NEXT: File Auxiliary Entry {
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
index db1e770e04a1e..c17b038a6960c 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
@@ -176,7 +176,7 @@ entry:
; SYM-NEXT: Value (SymbolTableIndex): 0x0
; SYM-NEXT: Section: N_DEBUG
; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
+; SYM-NEXT: CPU Version ID: TCPU_COM (0x3)
; SYM-NEXT: StorageClass: C_FILE (0x67)
; SYM-NEXT: NumberOfAuxEntries: 2
; SYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll
index 3387eef8e43cb..3b2917ec97284 100644
--- a/llvm/test/CodeGen/PowerPC/aix-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll
@@ -104,7 +104,7 @@ entry:
; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0
; CHECKSYM-NEXT: Section: N_DEBUG
; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; CHECKSYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
+; CHECKSYM-NEXT: CPU Version ID: TCPU_COM (0x3)
; CHECKSYM-NEXT: StorageClass: C_FILE (0x67)
; CHECKSYM-NEXT: NumberOfAuxEntries: 2
; CHECKSYM: Symbol {
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
index c6ac18c010902..7383c6c2f8445 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -163,7 +163,7 @@ declare i32 @bar(i32)
; SYM-NEXT: Value (SymbolTableIndex): 0x0
; SYM-NEXT: Section: N_DEBUG
; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9)
-; SYM-NEXT: CPU Version ID: TCPU_PWR (0x4)
+; SYM-NEXT: CPU Version ID: TCPU_COM (0x3)
; SYM-NEXT: StorageClass: C_FILE (0x67)
; SYM-NEXT: NumberOfAuxEntries: 2
; SYM-NEXT: File Auxiliary Entry {
diff --git a/llvm/tools/llvm-readobj/XCOFFDumper.cpp b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
index 5af29dc0134c7..6a099c08e1aca 100644
--- a/llvm/tools/llvm-readobj/XCOFFDumper.cpp
+++ b/llvm/tools/llvm-readobj/XCOFFDumper.cpp
@@ -723,12 +723,12 @@ const EnumEntry<XCOFF::CFileLangId> CFileLangIdClass[] = {
const EnumEntry<XCOFF::CFileCpuId> CFileCpuIdClass[] = {
#define ECase(X) \
{ #X, XCOFF::X }
- ECase(TCPU_INVALID), ECase(TCPU_PPC), ECase(TCPU_PPC64), ECase(TCPU_COM),
- ECase(TCPU_PWR), ECase(TCPU_ANY), ECase(TCPU_601), ECase(TCPU_603),
- ECase(TCPU_604), ECase(TCPU_620), ECase(TCPU_A35), ECase(TCPU_970),
- ECase(TCPU_PWR1), ECase(TCPU_PWR5), ECase(TCPU_PWR6), ECase(TCPU_VEC),
- ECase(TCPU_PWR5X), ECase(TCPU_PWR6E), ECase(TCPU_PWR7), ECase(TCPU_PWR8),
- ECase(TCPU_PWR9), ECase(TCPU_PWR10), ECase(TCPU_PWRX)
+ ECase(TCPU_INVALID), ECase(TCPU_PPC), ECase(TCPU_PPC64), ECase(TCPU_COM),
+ ECase(TCPU_PWR), ECase(TCPU_ANY), ECase(TCPU_601), ECase(TCPU_603),
+ ECase(TCPU_604), ECase(TCPU_620), ECase(TCPU_A35), ECase(TCPU_970),
+ ECase(TCPU_PWR5), ECase(TCPU_PWR6), ECase(TCPU_PWR5X), ECase(TCPU_PWR6E),
+ ECase(TCPU_PWR7), ECase(TCPU_PWR8), ECase(TCPU_PWR9), ECase(TCPU_PWR10),
+ ECase(TCPU_PWRX)
#undef ECase
};
>From 9fc8f96dd2eaf33563e9d501de97e33899c1eb22 Mon Sep 17 00:00:00 2001
From: esmeyi <esme.yi at ibm.com>
Date: Wed, 26 Jun 2024 02:04:29 -0400
Subject: [PATCH 7/7] Update test cases.
---
llvm/test/CodeGen/PowerPC/aix-filename-c.ll | 6 +++---
llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 2 +-
llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 2 +-
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
index ac5e03c158ca3..9f43e81dcdbf8 100644
--- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll
@@ -7,7 +7,7 @@
source_filename = "1.c"
-; ASM: .file "1.c",,"{{.*}}, LLVM version{{.*}}git"
+; ASM: .file "1.c",,"{{.*}}LLVM{{.*}}"
; ASM-NEXT: .machine "PWR9"
; ASM-NEXT: .csect ..text..[PR],5
; ASM-NEXT: .rename ..text..[PR],""
@@ -28,7 +28,7 @@ source_filename = "1.c"
; OBJ32-NEXT: }
; OBJ32-NEXT: File Auxiliary Entry {
; OBJ32-NEXT: Index: 2
-; OBJ32-NEXT: Name: {{.*}}, LLVM version{{.*}}git
+; OBJ32-NEXT: Name: {{.*}}LLVM{{.*}}
; OBJ32-NEXT: Type: XFT_CV (0x2)
; OBJ32-NEXT: }
; OBJ32-NEXT: }
@@ -50,7 +50,7 @@ source_filename = "1.c"
; OBJ64-NEXT: }
; OBJ64-NEXT: File Auxiliary Entry {
; OBJ64-NEXT: Index: 2
-; OBJ64-NEXT: Name: {{.*}}, LLVM version{{.*}}git
+; OBJ64-NEXT: Name: {{.*}}LLVM{{.*}}
; OBJ64-NEXT: Type: XFT_CV (0x2)
; OBJ64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
; OBJ64-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
index ebd7c193a7f4c..288d17b4fd47b 100644
--- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
@@ -27,7 +27,7 @@ entry:
; CHECK-NEXT: }
; CHECK-NEXT: File Auxiliary Entry {
; CHECK-NEXT: Index: 2
-; CHECK-NEXT: Name: {{.*}}, LLVM version{{.*}}git
+; CHECK-NEXT: Name: {{.*}}LLVM{{.*}}
; CHECK-NEXT: Type: XFT_CV (0x2)
; CHECK-NEXT: }
; CHECK-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
index a35299a6fbd8b..6f6c9e952b277 100644
--- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
@@ -225,7 +225,7 @@ entry:
; SYM-NEXT: }
; SYM-NEXT: File Auxiliary Entry {
; SYM-NEXT: Index: 2
-; SYM-NEXT: Name: {{.*}}, LLVM version{{.*}}git
+; SYM-NEXT: Name: {{.*}}LLVM{{.*}}
; SYM-NEXT: Type: XFT_CV (0x2)
; SYM-NEXT: }
; SYM-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
index d9cd60a4a0540..e4cb470168079 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
@@ -224,7 +224,7 @@
; SYMS-NEXT: }
; SYMS-NEXT: File Auxiliary Entry {
; SYMS-NEXT: Index: 2
-; SYMS-NEXT: Name: {{.*}}, LLVM version{{.*}}git
+; SYMS-NEXT: Name: {{.*}}LLVM{{.*}}
; SYMS-NEXT: Type: XFT_CV (0x2)
; SYMS64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
; SYMS-NEXT: }
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
index 7383c6c2f8445..04115b269e8ab 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
@@ -174,7 +174,7 @@ declare i32 @bar(i32)
; SYM-NEXT: }
; SYM-NEXT: File Auxiliary Entry {
; SYM-NEXT: Index: 2
-; SYM-NEXT: Name: {{.*}}, LLVM version{{.*}}git
+; SYM-NEXT: Name: {{.*}}LLVM{{.*}}
; SYM-NEXT: Type: XFT_CV (0x2)
; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC)
; SYM-NEXT: }
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