[llvm] [AMDGPU] Set register bank for i1 arguments/return values (PR #96155)

[Jun Wang via llvm-commits]

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@@ -3745,6 +3745,21 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     if (!DstBank)
       DstBank = SrcBank;
 
+    // The calling convention is to be updated such that i1 function arguments
+    // or return values are assigned to SGPRs without promoting to i32. With
+    // this, for i1 function arguments, the call of getRegBank() above gives
+    // incorrect result. We set both src and dst banks to VCCRegBank.
+    if (!MI.getOperand(1).getReg().isVirtual() &&
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jwanggit86 wrote:

Actually, once the calling convention for i1 arg is changed, we would have instructions such as `%0:_(s1) = COPY $sgpr4_sgpr5`. For this instruction, after the 2 calls of `getRegBank()`, `DstBank` is null, and `SrcBank` is `SGPRRegBank`. We want both to be `VCCRegBank`, hence the patch.

The reason it returns `SGPRRegBank` instead of `VCCRegBank` is because of a flaw in `RegisterBankInfo::getRegBank()`, as follows:
```C
const RegisterBank *
RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
                             const TargetRegisterInfo &TRI) const {
  if (!Reg.isVirtual()) {
    // FIXME: This was probably a copy to a virtual register that does have a
    // type we could use.
    const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg, TRI);
    return RC ? &getRegBankFromRegClass(*RC, LLT()) : nullptr;  
  }
...
```
Note that there's a FIXME. In the call of `getRegBankFromRegClass` it passes the default type `LLT()`, which is not what we want here.
The IF statement in the patch basically says, if the src is physical and dst type is s1, then set the reg bank to VCCRegBank, which corrects the problem.

https://github.com/llvm/llvm-project/pull/96155