[llvm] dff6871 - [RISCV][GISel] Support G_FCONSTANT for Zfh.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 14:30:53 PDT 2024
Author: Craig Topper
Date: 2024-06-25T14:10:25-07:00
New Revision: dff6871cdbce8569a141d541023061294860fb95
URL: https://github.com/llvm/llvm-project/commit/dff6871cdbce8569a141d541023061294860fb95
DIFF: https://github.com/llvm/llvm-project/commit/dff6871cdbce8569a141d541023061294860fb95.diff
LOG: [RISCV][GISel] Support G_FCONSTANT for Zfh.
Added:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index a091380e8ce82..53b2c7e196899 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -577,12 +577,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
const APFloat &FPimm = MI.getOperand(1).getFPImm()->getValueAPF();
APInt Imm = FPimm.bitcastToAPInt();
unsigned Size = MRI.getType(DstReg).getSizeInBits();
- if (Size == 32 || (Size == 64 && Subtarget->is64Bit())) {
+ if (Size == 16 || Size == 32 || (Size == 64 && Subtarget->is64Bit())) {
Register GPRReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB))
return false;
- unsigned Opcode = Size == 64 ? RISCV::FMV_D_X : RISCV::FMV_W_X;
+ unsigned Opcode = Size == 64 ? RISCV::FMV_D_X
+ : Size == 32 ? RISCV::FMV_W_X
+ : RISCV::FMV_H_X;
auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg});
if (!FMV.constrainAllUses(TII, TRI, RBI))
return false;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index bec542f7781b1..122b742c52ee9 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -410,9 +410,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder(G_IS_FPCLASS)
.customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
- getActionDefinitionsBuilder(G_FCONSTANT)
- .legalIf(typeIsScalarFPArith(0, ST))
- .lowerFor({s32, s64});
+ auto &FConstantActions = getActionDefinitionsBuilder(G_FCONSTANT)
+ .legalIf(typeIsScalarFPArith(0, ST));
+ if (ST.hasStdExtZfh())
+ FConstantActions.legalFor({s16});
+ FConstantActions.lowerFor({s32, s64});
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir
new file mode 100644
index 0000000000000..8951e373ba7a9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-constant-f16.mir
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64
+
+---
+name: half_imm
+legalized: true
+regBankSelected: true
+body: |
+ bb.1:
+ ; RV32-LABEL: name: half_imm
+ ; RV32: [[LUI:%[0-9]+]]:gpr = LUI 4
+ ; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 584
+ ; RV32-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDI]]
+ ; RV32-NEXT: $f10_h = COPY [[FMV_H_X]]
+ ; RV32-NEXT: PseudoRET implicit $f10_h
+ ;
+ ; RV64-LABEL: name: half_imm
+ ; RV64: [[LUI:%[0-9]+]]:gpr = LUI 4
+ ; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 584
+ ; RV64-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[ADDIW]]
+ ; RV64-NEXT: $f10_h = COPY [[FMV_H_X]]
+ ; RV64-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = G_FCONSTANT half 0xH4248
+ $f10_h = COPY %0(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: half_imm_op
+legalized: true
+regBankSelected: true
+body: |
+ bb.1:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: half_imm_op
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 15
+ ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 10
+ ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[SLLI]]
+ ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[FMV_H_X]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FADD_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = G_FCONSTANT half 1.000000e+00
+ %2:fprb(s16) = G_FADD %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: half_positive_zero
+legalized: true
+regBankSelected: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: half_positive_zero
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+ ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:fprb(s16) = G_FCONSTANT half 0.000000e+00
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: half_negative_zero
+legalized: true
+regBankSelected: true
+body: |
+ bb.1:
+ liveins: $x10
+
+ ; CHECK-LABEL: name: half_negative_zero
+ ; CHECK: liveins: $x10
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1048568
+ ; CHECK-NEXT: [[FMV_H_X:%[0-9]+]]:fpr16 = FMV_H_X [[LUI]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMV_H_X]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %1:fprb(s16) = G_FCONSTANT half -0.000000e+00
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
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