[llvm] [RISCV][GISel] Support fcmp and fclass for Zfh. (PR #96696)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 13:50:10 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
---
Patch is 60.51 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/96696.diff
15 Files Affected:
- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+5-5)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+12-5)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp (-1)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir (+355)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir (+355)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv32.mir (+82)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv64.mir (+82)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv32.mir (+312)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fcmp-f16-rv64.mir (+312)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv32.mir (+28)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-is-fpclass-f16-rv64.mir (+28)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv32.mir (+27)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fcmp-f16-rv64.mir (+27)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv32.mir (+31)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/is-fpclass-f16-rv64.mir (+31)
``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index a091380e8ce82..af0f22c5c5234 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1146,16 +1146,16 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
// Convert an FCMP predicate to one of the supported F or D instructions.
static unsigned getFCmpOpcode(CmpInst::Predicate Pred, unsigned Size) {
- assert((Size == 32 || Size == 64) && "Unsupported size");
+ assert((Size == 16 || Size == 32 || Size == 64) && "Unsupported size");
switch (Pred) {
default:
llvm_unreachable("Unsupported predicate");
case CmpInst::FCMP_OLT:
- return Size == 32 ? RISCV::FLT_S : RISCV::FLT_D;
+ return Size == 16 ? RISCV::FLT_H : Size == 32 ? RISCV::FLT_S : RISCV::FLT_D;
case CmpInst::FCMP_OLE:
- return Size == 32 ? RISCV::FLE_S : RISCV::FLE_D;
+ return Size == 16 ? RISCV::FLE_H : Size == 32 ? RISCV::FLE_S : RISCV::FLE_D;
case CmpInst::FCMP_OEQ:
- return Size == 32 ? RISCV::FEQ_S : RISCV::FEQ_D;
+ return Size == 16 ? RISCV::FEQ_H : Size == 32 ? RISCV::FEQ_S : RISCV::FEQ_D;
}
}
@@ -1207,7 +1207,7 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
Register RHS = CmpMI.getRHSReg();
unsigned Size = MRI.getType(LHS).getSizeInBits();
- assert((Size == 32 || Size == 64) && "Unexpected size");
+ assert((Size == 16 || Size == 32 || Size == 64) && "Unexpected size");
Register TmpReg = DstReg;
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index bec542f7781b1..0c9d72ae96a0f 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -402,13 +402,20 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
typeIs(1, s32)(Query));
});
- getActionDefinitionsBuilder(G_FCMP)
- .legalIf(all(typeIs(0, sXLen), typeIsScalarFPArith(1, ST)))
- .clampScalar(0, sXLen, sXLen);
+ auto &FCmpActions = getActionDefinitionsBuilder(G_FCMP).legalIf(
+ all(typeIs(0, sXLen), typeIsScalarFPArith(1, ST)));
+ // TODO: Fold this into typeIsScalarFPArith.
+ if (ST.hasStdExtZfh())
+ FCmpActions.legalFor({sXLen, s16});
+ FCmpActions.clampScalar(0, sXLen, sXLen);
// TODO: Support vector version of G_IS_FPCLASS.
- getActionDefinitionsBuilder(G_IS_FPCLASS)
- .customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
+ auto &FClassActions =
+ getActionDefinitionsBuilder(G_IS_FPCLASS)
+ .customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
+ // TODO: Fold this into typeIsScalarFPArith.
+ if (ST.hasStdExtZfh())
+ FClassActions.customFor({s1, s16});
getActionDefinitionsBuilder(G_FCONSTANT)
.legalIf(typeIsScalarFPArith(0, ST))
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 41ca164b38f3d..d25e96525399e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -478,7 +478,6 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
LLT Ty = MRI.getType(MI.getOperand(2).getReg());
unsigned Size = Ty.getSizeInBits();
- assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
OpdsMapping[0] = GPRValueMapping;
OpdsMapping[2] = OpdsMapping[3] = getFPValueMapping(Size);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir
new file mode 100644
index 0000000000000..6fdfd65a15f00
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv32.mir
@@ -0,0 +1,355 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fcmp_oeq_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_oeq_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = nofpexcept FEQ_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[FEQ_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ogt_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ogt_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FLT_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_oge_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_oge_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FLE_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(oge), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_olt_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_olt_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = nofpexcept FLT_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[FLT_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(olt), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ole_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ole_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = nofpexcept FLE_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[FLE_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(ole), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_one_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_one_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(one), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ord_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ord_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]]
+ ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(ord), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ueq_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ueq_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]]
+ ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[OR]], 1
+ ; CHECK-NEXT: $x10 = COPY [[XORI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ugt_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ugt_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1
+ ; CHECK-NEXT: $x10 = COPY [[XORI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_uge_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_uge_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1
+ ; CHECK-NEXT: $x10 = COPY [[XORI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(uge), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ult_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ult_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLE_H]], 1
+ ; CHECK-NEXT: $x10 = COPY [[XORI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(ult), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ule_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ule_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FLT_H]], 1
+ ; CHECK-NEXT: $x10 = COPY [[XORI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(ule), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_une_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_une_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[FEQ_H]], 1
+ ; CHECK-NEXT: $x10 = COPY [[XORI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(une), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_uno_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_uno_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = FEQ_H [[COPY]], [[COPY]]
+ ; CHECK-NEXT: [[FEQ_H1:%[0-9]+]]:gpr = FEQ_H [[COPY1]], [[COPY1]]
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[FEQ_H]], [[FEQ_H1]]
+ ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[AND]], 1
+ ; CHECK-NEXT: $x10 = COPY [[XORI]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s32) = G_FCMP floatpred(uno), %0(s16), %1
+ $x10 = COPY %4(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir
new file mode 100644
index 0000000000000..827d3e567e6f1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fcmp-f16-rv64.mir
@@ -0,0 +1,355 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fcmp_oeq_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_oeq_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FEQ_H:%[0-9]+]]:gpr = nofpexcept FEQ_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[FEQ_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s64) = G_FCMP floatpred(oeq), %0(s16), %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ogt_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ogt_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FLT_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s64) = G_FCMP floatpred(ogt), %0(s16), %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_oge_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_oge_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = FLE_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: $x10 = COPY [[FLE_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s64) = G_FCMP floatpred(oge), %0(s16), %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_olt_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_olt_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = nofpexcept FLT_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[FLT_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s64) = G_FCMP floatpred(olt), %0(s16), %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ole_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ole_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLE_H:%[0-9]+]]:gpr = nofpexcept FLE_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[FLE_H]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s64) = G_FCMP floatpred(ole), %0(s16), %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_one_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_one_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FLT_H:%[0-9]+]]:gpr = FLT_H [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[FLT_H1:%[0-9]+]]:gpr = FLT_H [[COPY1]], [[COPY]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:gpr = OR [[FLT_H]], [[FLT_H1]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]]
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %4:gprb(s64) = G_FCMP floatpred(one), %0(s16), %1
+ $x10 = COPY %4(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: fcmp_ord_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcmp_ord_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/96696
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