[llvm] a55dc1d - [SLP][NFC]Add a test with the incorrect casting of the sext/zext alternate node, NFC.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2024-06-25T12:34:30-07:00
New Revision: a55dc1d3ca2ed948bdae887ea1f4ab8041ed1b6d

URL: https://github.com/llvm/llvm-project/commit/a55dc1d3ca2ed948bdae887ea1f4ab8041ed1b6d
DIFF: https://github.com/llvm/llvm-project/commit/a55dc1d3ca2ed948bdae887ea1f4ab8041ed1b6d.diff

LOG: [SLP][NFC]Add a test with the incorrect casting of the sext/zext alternate node, NFC.

Added: 
    

Modified: 
    llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
index c83d9363c1809..9d7cf368fbc3f 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/shuffled-gather-casted.ll
@@ -53,3 +53,58 @@ entry:
   ret i32 %max.3
 }
 
+define i32 @test1(ptr %p) {
+; CHECK-LABEL: define i32 @test1(
+; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[D_0:%.*]] = load i16, ptr [[P]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i16> <i16 0, i16 poison, i16 0, i16 0>, i16 [[D_0]], i32 1
+; CHECK-NEXT:    [[TMP1:%.*]] = or <4 x i16> [[TMP0]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = and <4 x i16> [[TMP1]], <i16 -16383, i16 -1, i16 -1, i16 -1>
+; CHECK-NEXT:    [[TMP3:%.*]] = zext <4 x i16> [[TMP0]] to <4 x i32>
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i32> <i32 49153, i32 65535, i32 65535, i32 65535>, <4 x i32> [[TMP3]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq <4 x i32> [[TMP4]], <i32 -16383, i32 65535, i32 65535, i32 65535>
+; CHECK-NEXT:    [[TMP6:%.*]] = select <4 x i1> [[TMP5]], <4 x i16> [[TMP2]], <4 x i16> <i16 3, i16 4, i16 2, i16 1>
+; CHECK-NEXT:    [[TMP7:%.*]] = zext <4 x i16> [[TMP6]] to <4 x i32>
+; CHECK-NEXT:    [[TMP8:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP7]])
+; CHECK-NEXT:    ret i32 [[TMP8]]
+;
+entry:
+  %d.0 = load i16, ptr %p, align 4
+  %zext.d.0 = zext i16 %d.0 to i32
+  %zero.0 = zext i16 0 to i32
+  %zero.1 = zext i16 0 to i32
+  %zero.2 = zext i16 0 to i32
+
+  %or.d.0 = or i32 %zext.d.0, 0
+  %or.zero.0 = or i32 %zero.0, 0
+  %or.zero.1 = or i32 %zero.1, 0
+  %or.zero.2 = or i32 %zero.2, 0
+
+  %szero.00 = sext i16 65535 to i32
+  %szero.0 = sext i16 -16383 to i32
+  %uzero.1 = zext i16 65535 to i32
+  %szero.2 = sext i16 65535 to i32
+
+  %zero.d.0 = and i32 %or.d.0, %szero.00
+  %and.zero.0 = and i32 %or.zero.0, %szero.0
+  %and.zero.1 = and i32 %or.zero.1, %uzero.1
+  %and.zero.2 = and i32 %or.zero.2, %szero.2
+
+  %d.0.gt.0 = icmp eq i32 %zext.d.0, 65535
+  %false.0 = icmp eq i32 %szero.0, -16383
+  %false.1 = icmp eq i32 %uzero.1, 65535
+  %false.2 = icmp eq i32 %szero.2, 65535
+
+  %select.0.2 = select i1 %d.0.gt.0, i32 %zero.d.0, i32 4
+  %select.1.0 = select i1 %false.0, i32 %and.zero.0, i32 3
+  %select.2.0 = select i1 %false.1, i32 %and.zero.1, i32 2
+  %select.3.0 = select i1 %false.2, i32 %and.zero.2, i32 1
+
+  %max.0 = add i32 %select.0.2, %select.1.0
+  %max.1 = add i32 %max.0, %select.2.0
+  %max.2 = add i32 %max.1, %select.3.0
+
+  ret i32 %max.2
+}
+