[llvm] [llvm][CodeGen] Update checking method of loop-carried phi in window scheduler (PR #96288)
Hua Tian via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 05:01:03 PDT 2024
=?utf-8?b?4oCcYWtpcmF0aWFu4oCd?= <akiratian at tencent.com>,
=?utf-8?b?4oCcYWtpcmF0aWFu4oCd?= <akiratian at tencent.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/96288 at github.com>
https://github.com/huaatian updated https://github.com/llvm/llvm-project/pull/96288
>From a914a12c3eb73d11c6e891ffd47a7accd5d3c8da Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Cakiratian=E2=80=9D?= <akiratian at tencent.com>
Date: Fri, 21 Jun 2024 16:00:40 +0800
Subject: [PATCH 1/3] [llvm][CodeGen] Update checking method of loop-carried
phi in window scheduler
Added some logic to check loop-carried phis in the window scheduler. It
now includes the scenario where the preceding phi uses the virtual
register defined by the succeeding phi.
---
llvm/lib/CodeGen/WindowScheduler.cpp | 36 +++++++++----
llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir | 3 +-
llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir | 7 +--
llvm/test/CodeGen/Hexagon/swp-ws-exp.mir | 3 +-
llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir | 9 ++--
llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir | 14 +++--
llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir | 3 +-
llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir | 52 +++++++++++++++++++
.../CodeGen/Hexagon/swp-ws-meta-instr.mir | 3 +-
llvm/test/CodeGen/Hexagon/swp-ws-phi.mir | 3 +-
llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir | 3 +-
llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir | 3 +-
12 files changed, 109 insertions(+), 30 deletions(-)
create mode 100644 llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 7a86351a1f4e3..e658bb861768b 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -192,22 +192,36 @@ bool WindowScheduler::initialize() {
return false;
}
// Check each MI in MBB.
- SmallVector<Register, 8> PhiDefs;
+ SmallSet<Register, 8> PrevDefs;
+ SmallSet<Register, 8> PrevUses;
+ auto IsLoopCarried = [&](MachineInstr &Phi) {
+ // Two cases are checked here: (1)The virtual register defined by the
+ // preceding phi is used by the succeeding phi;(2)The preceding phi uses the
+ // virtual register defined by the succeeding phi.
+ for (auto MO : Phi.operands()) {
+ if (!MO.isReg())
+ continue;
+ if (MO.isDef()) {
+ if (PrevUses.count(MO.getReg()))
+ return true;
+ PrevDefs.insert(MO.getReg());
+ } else if (MO.isUse()) {
+ if (PrevDefs.count(MO.getReg()))
+ return true;
+ PrevUses.insert(MO.getReg());
+ }
+ }
+ return false;
+ };
auto PLI = TII->analyzeLoopForPipelining(MBB);
for (auto &MI : *MBB) {
if (MI.isMetaInstruction() || MI.isTerminator())
continue;
if (MI.isPHI()) {
- for (auto Def : PhiDefs)
- if (MI.readsRegister(Def, TRI)) {
- LLVM_DEBUG(
- dbgs()
- << "Consecutive phis are not allowed in window scheduling!\n");
- return false;
- }
- for (auto Def : MI.defs())
- if (Def.isReg())
- PhiDefs.push_back(Def.getReg());
+ if (IsLoopCarried(MI)) {
+ LLVM_DEBUG(dbgs() << "Loop carried phis are not supported yet!\n");
+ return false;
+ }
++SchedPhiNum;
++BestOffset;
} else
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir b/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir
index b1549e39c910f..9645ced56452e 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-dead-def.mir
@@ -1,6 +1,7 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
# CHECK-LABEL: name: exp_approx_top_six
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir b/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir
index b62cbbbb8af4e..a6285445d85db 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-exp-dbg.mir
@@ -1,11 +1,12 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s
-#
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
+
# The Window Scheduling algorithm will discard the debug IR, just like the SMS
# algorithm does. Additionally, the MMO information in the IR is also preserved
# to ensure that no barrier dependencies are generated within the loop body.
-#
+
# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
# CHECK-LABEL: name: exp_approx
# CHECK: bb.5.for.body:
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir b/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
index 534c25591f5bf..278663543ed4f 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-exp.mir
@@ -1,6 +1,7 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
index 1721419cea9db..447918dec825d 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-0.mir
@@ -1,13 +1,14 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s \
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s \
# RUN: --check-prefix=CHECK-INITIALIZE
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -window-region-limit=1 -window-ii-limit=1 -o - \
-# RUN: 2>&1 | FileCheck %s --check-prefix=CHECK-ANALYSE-II
+# RUN: -window-sched=force -window-region-limit=1 -window-ii-limit=1 \
+# RUN: -filetype=null 2>&1 | FileCheck %s --check-prefix=CHECK-ANALYSE-II
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
# RUN: -window-sched=force -window-region-limit=1 -window-search-ratio=80 \
-# RUN: -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SCHED-NOT-NEEDED
+# RUN: -filetype=null 2>&1 | FileCheck %s --check-prefix=CHECK-SCHED-NOT-NEEDED
# CHECK-INITIALIZE: There are too few MIs in the window region!
# CHECK-INITIALIZE: The WindowScheduler failed to initialize!
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir
index d0521a92585b0..2b9e790776c2b 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-1.mir
@@ -1,10 +1,14 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s \
-# RUN: --check-prefix=CHECK-SUCCESSIVE-PHI
-
-# CHECK-SUCCESSIVE-PHI: Consecutive phis are not allowed in window scheduling!
-# CHECK-SUCCESSIVE-PHI: The WindowScheduler failed to initialize!
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
+
+# CHECK: Loop carried phis are not supported yet!
+# CHECK: The WindowScheduler failed to initialize!
+# CHECK-LABEL: body: |
+# CHECK: bb.3 (machine-block-address-taken):
+# CHECK: [[REG:%[0-9]+]]:intregs = PHI {{%[0-9]+}}, %bb.1, {{%[0-9]+}}, %bb.3
+# CHECK: {{%[0-9]+}}:intregs = PHI {{%[0-9]+}}, %bb.1, [[REG]], %bb.3
---
name: relu
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir
index 64229fd8d75cf..601b98dca8e20 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-2.mir
@@ -1,6 +1,7 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
# CHECK: The WindowScheduler failed to initialize!
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir b/llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir
new file mode 100644
index 0000000000000..b56c69d4e352f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-fail-3.mir
@@ -0,0 +1,52 @@
+# REQUIRES: asserts
+# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
+
+# CHECK: Loop carried phis are not supported yet!
+# CHECK: The WindowScheduler failed to initialize!
+# CHECK-LABEL: body: |
+# CHECK: bb.3 (machine-block-address-taken):
+# CHECK: {{%[0-9]+}}:intregs = PHI {{%[0-9]+}}, %bb.1, [[REG:%[0-9]+]], %bb.3
+# CHECK: [[REG]]:intregs = PHI {{%[0-9]+}}, %bb.1, {{%[0-9]+}}, %bb.3
+
+---
+name: relu
+tracksRegLiveness: true
+body: |
+ bb.0:
+ successors: %bb.2(0x30000000), %bb.1(0x50000000)
+ liveins: $r0, $r1, $r2
+
+ %0:intregs = COPY $r2
+ %1:intregs = COPY $r1
+ %2:intregs = COPY $r0
+ %3:predregs = C2_cmpeqi %2, 0
+ J2_jumpt killed %3, %bb.2, implicit-def dead $pc
+ J2_jump %bb.1, implicit-def dead $pc
+
+ bb.1:
+ successors: %bb.3(0x80000000)
+
+ %4:hvxvr = V6_vd0
+ %5:intregs = A2_addi %2, 31
+ %6:intregs = S2_lsr_i_r %5, 5
+ %7:intregs = COPY %6
+ J2_loop0r %bb.3, %7, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+ J2_jump %bb.3, implicit-def dead $pc
+
+ bb.2:
+ PS_jmpret $r31, implicit-def dead $pc
+
+ bb.3 (machine-block-address-taken):
+ successors: %bb.3(0x7c000000), %bb.2(0x04000000)
+
+ %8:intregs = PHI %0, %bb.1, %9, %bb.3
+ %9:intregs = PHI %1, %bb.1, %10, %bb.3
+ %11:hvxvr, %10:intregs = V6_vL32b_pi %9, 128
+ %12:hvxvr = V6_vmaxw killed %11, %4
+ %13:intregs = V6_vS32b_pi %8, 128, killed %12
+ ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+ J2_jump %bb.2, implicit-def dead $pc
+
+...
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir b/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir
index f12a72790741c..ca6a87119b1d6 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-meta-instr.mir
@@ -1,6 +1,7 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
# CHECK-NOT: PSEUDO_PROBE
# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir b/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir
index 7897a02b43f38..a0d3e95190f06 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-phi.mir
@@ -1,6 +1,7 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -filetype=null 2>&1 | FileCheck %s
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
# CHECK: Window scheduling is not needed!
# CHECK-LABEL: body: |
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir b/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir
index 1e764d5fa48b4..555608831c4d1 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-sqrt.mir
@@ -1,6 +1,7 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -o - 2>&1 | FileCheck %s
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir b/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
index 1eb0afbcf8c21..b1720be689c09 100644
--- a/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
@@ -1,6 +1,7 @@
# REQUIRES: asserts
# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
-# RUN: -window-sched=force -filetype=null 2>&1 | FileCheck %s
+# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
+# RUN: | FileCheck %s
# CHECK: SU(3): Ord Latency=0 Weak
# CHECK: SU(1): Ord Latency=0 Weak
>From b4f725b9b881fcf563bf881197e15ff765a59dc5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Cakiratian=E2=80=9D?= <akiratian at tencent.com>
Date: Fri, 21 Jun 2024 19:47:02 +0800
Subject: [PATCH 2/3] [llvm][CodeGen] Modifications made based on review
comments 1
---
llvm/lib/CodeGen/WindowScheduler.cpp | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index e658bb861768b..ca118cc3f6f3c 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -198,17 +198,18 @@ bool WindowScheduler::initialize() {
// Two cases are checked here: (1)The virtual register defined by the
// preceding phi is used by the succeeding phi;(2)The preceding phi uses the
// virtual register defined by the succeeding phi.
- for (auto MO : Phi.operands()) {
- if (!MO.isReg())
- continue;
- if (MO.isDef()) {
- if (PrevUses.count(MO.getReg()))
- return true;
- PrevDefs.insert(MO.getReg());
- } else if (MO.isUse()) {
- if (PrevDefs.count(MO.getReg()))
+ auto Def = Phi.getOperand(0);
+ if (Def.isReg()) {
+ if (PrevUses.count(Def.getReg()))
+ return true;
+ PrevDefs.insert(Def.getReg());
+ }
+ for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
+ auto Use = Phi.getOperand(I);
+ if (Use.isReg()) {
+ if (PrevDefs.count(Use.getReg()))
return true;
- PrevUses.insert(MO.getReg());
+ PrevUses.insert(Use.getReg());
}
}
return false;
>From 8bea9bc54e0a1e15f6f7411c3b71b2543d712630 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Cakiratian=E2=80=9D?= <akiratian at tencent.com>
Date: Tue, 25 Jun 2024 19:59:27 +0800
Subject: [PATCH 3/3] [llvm][CodeGen] Modifications made based on review
comments 2
---
llvm/lib/CodeGen/WindowScheduler.cpp | 18 ++++++------------
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index ca118cc3f6f3c..0777480499e55 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -198,19 +198,13 @@ bool WindowScheduler::initialize() {
// Two cases are checked here: (1)The virtual register defined by the
// preceding phi is used by the succeeding phi;(2)The preceding phi uses the
// virtual register defined by the succeeding phi.
- auto Def = Phi.getOperand(0);
- if (Def.isReg()) {
- if (PrevUses.count(Def.getReg()))
- return true;
- PrevDefs.insert(Def.getReg());
- }
+ if (PrevUses.count(Phi.getOperand(0).getReg()))
+ return true;
+ PrevDefs.insert(Phi.getOperand(0).getReg());
for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
- auto Use = Phi.getOperand(I);
- if (Use.isReg()) {
- if (PrevDefs.count(Use.getReg()))
- return true;
- PrevUses.insert(Use.getReg());
- }
+ if (PrevDefs.count(Phi.getOperand(I).getReg()))
+ return true;
+ PrevUses.insert(Phi.getOperand(I).getReg());
}
return false;
};
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