[llvm] [AMDGPU][NFC] Rename AMDGPUVariadicMCExpr to AMDGPUMCExpr. (PR #96618)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 03:49:31 PDT 2024
https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/96618
Some of our custom expressions are not variadic and there seems to be little benefit in mentioning the variadic nature of expression nodes in the name anyway.
>From ebc0cde79e513ddc6995d28d9fd54b79e8401268 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Tue, 25 Jun 2024 11:25:59 +0100
Subject: [PATCH] [AMDGPU][NFC] Rename AMDGPUVariadicMCExpr to AMDGPUMCExpr.
Some of our custom expressions are not variadic and there seems
to be little benefit in mentioning the variadic nature of
expression nodes in the name anyway.
---
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 37 ++++---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 4 +-
.../AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp | 96 +++++++++----------
.../Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h | 58 ++++++-----
4 files changed, 93 insertions(+), 102 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index d8e22f4b0d8fa..cf51a8a80c0c8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -793,7 +793,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
// The calculations related to SGPR/VGPR blocks are
// duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
// unified.
- const MCExpr *ExtraSGPRs = AMDGPUVariadicMCExpr::createExtraSGPRs(
+ const MCExpr *ExtraSGPRs = AMDGPUMCExpr::createExtraSGPRs(
ProgInfo.VCCUsed, ProgInfo.FlatUsed,
getTargetStreamer()->getTargetID()->isXnackOnOrAny(), Ctx);
@@ -886,27 +886,27 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
}
}
}
- ProgInfo.NumSGPR = AMDGPUVariadicMCExpr::createMax(
+ ProgInfo.NumSGPR = AMDGPUMCExpr::createMax(
{ProgInfo.NumSGPR, CreateExpr(WaveDispatchNumSGPR)}, Ctx);
- ProgInfo.NumArchVGPR = AMDGPUVariadicMCExpr::createMax(
+ ProgInfo.NumArchVGPR = AMDGPUMCExpr::createMax(
{ProgInfo.NumVGPR, CreateExpr(WaveDispatchNumVGPR)}, Ctx);
- ProgInfo.NumVGPR = AMDGPUVariadicMCExpr::createTotalNumVGPR(
+ ProgInfo.NumVGPR = AMDGPUMCExpr::createTotalNumVGPR(
ProgInfo.NumAccVGPR, ProgInfo.NumArchVGPR, Ctx);
}
// Adjust number of registers used to meet default/requested minimum/maximum
// number of waves per execution unit request.
unsigned MaxWaves = MFI->getMaxWavesPerEU();
- ProgInfo.NumSGPRsForWavesPerEU = AMDGPUVariadicMCExpr::createMax(
- {ProgInfo.NumSGPR, CreateExpr(1ul),
- CreateExpr(STM.getMinNumSGPRs(MaxWaves))},
- Ctx);
- ProgInfo.NumVGPRsForWavesPerEU = AMDGPUVariadicMCExpr::createMax(
- {ProgInfo.NumVGPR, CreateExpr(1ul),
- CreateExpr(STM.getMinNumVGPRs(MaxWaves))},
- Ctx);
+ ProgInfo.NumSGPRsForWavesPerEU =
+ AMDGPUMCExpr::createMax({ProgInfo.NumSGPR, CreateExpr(1ul),
+ CreateExpr(STM.getMinNumSGPRs(MaxWaves))},
+ Ctx);
+ ProgInfo.NumVGPRsForWavesPerEU =
+ AMDGPUMCExpr::createMax({ProgInfo.NumVGPR, CreateExpr(1ul),
+ CreateExpr(STM.getMinNumVGPRs(MaxWaves))},
+ Ctx);
if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
STM.hasSGPRInitBug()) {
@@ -955,10 +955,9 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
unsigned Granule) {
const MCExpr *OneConst = CreateExpr(1ul);
const MCExpr *GranuleConst = CreateExpr(Granule);
- const MCExpr *MaxNumGPR =
- AMDGPUVariadicMCExpr::createMax({NumGPR, OneConst}, Ctx);
+ const MCExpr *MaxNumGPR = AMDGPUMCExpr::createMax({NumGPR, OneConst}, Ctx);
const MCExpr *AlignToGPR =
- AMDGPUVariadicMCExpr::createAlignTo(MaxNumGPR, GranuleConst, Ctx);
+ AMDGPUMCExpr::createAlignTo(MaxNumGPR, GranuleConst, Ctx);
const MCExpr *DivGPR =
MCBinaryExpr::createDiv(AlignToGPR, GranuleConst, Ctx);
const MCExpr *SubGPR = MCBinaryExpr::createSub(DivGPR, OneConst, Ctx);
@@ -1000,7 +999,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
// The MCExpr equivalent of divideCeil.
auto DivideCeil = [&Ctx](const MCExpr *Numerator, const MCExpr *Denominator) {
const MCExpr *Ceil =
- AMDGPUVariadicMCExpr::createAlignTo(Numerator, Denominator, Ctx);
+ AMDGPUMCExpr::createAlignTo(Numerator, Denominator, Ctx);
return MCBinaryExpr::createDiv(Ceil, Denominator, Ctx);
};
@@ -1073,7 +1072,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT);
}
- ProgInfo.Occupancy = AMDGPUVariadicMCExpr::createOccupancy(
+ ProgInfo.Occupancy = AMDGPUMCExpr::createOccupancy(
STM.computeOccupancy(F, ProgInfo.LDSSize), ProgInfo.NumSGPRsForWavesPerEU,
ProgInfo.NumVGPRsForWavesPerEU, STM, Ctx);
@@ -1265,8 +1264,8 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
// ScratchSize is in bytes, 16 aligned.
MD->setScratchSize(
CC,
- AMDGPUVariadicMCExpr::createAlignTo(CurrentProgramInfo.ScratchSize,
- MCConstantExpr::create(16, Ctx), Ctx),
+ AMDGPUMCExpr::createAlignTo(CurrentProgramInfo.ScratchSize,
+ MCConstantExpr::create(16, Ctx), Ctx),
Ctx);
if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 8c7b33fd0194a..ca5ac163325d8 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -8357,7 +8357,7 @@ void AMDGPUAsmParser::onBeginOfFile() {
/// max(expr, ...)
///
bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
- using AGVK = AMDGPUVariadicMCExpr::VariadicKind;
+ using AGVK = AMDGPUMCExpr::VariantKind;
if (isToken(AsmToken::Identifier)) {
StringRef TokenId = getTokenStr();
@@ -8387,7 +8387,7 @@ bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
"mismatch of commas in " + Twine(TokenId) + " expression");
return true;
}
- Res = AMDGPUVariadicMCExpr::create(VK, Exprs, getContext());
+ Res = AMDGPUMCExpr::create(VK, Exprs, getContext());
return false;
}
const MCExpr *Expr;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
index 159664faf983f..83fbf4ac53d50 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
@@ -21,13 +21,11 @@
using namespace llvm;
using namespace llvm::AMDGPU;
-AMDGPUVariadicMCExpr::AMDGPUVariadicMCExpr(VariadicKind Kind,
- ArrayRef<const MCExpr *> Args,
- MCContext &Ctx)
+AMDGPUMCExpr::AMDGPUMCExpr(VariantKind Kind, ArrayRef<const MCExpr *> Args,
+ MCContext &Ctx)
: Kind(Kind), Ctx(Ctx) {
assert(Args.size() >= 1 && "Needs a minimum of one expression.");
- assert(Kind != AGVK_None &&
- "Cannot construct AMDGPUVariadicMCExpr of kind none.");
+ assert(Kind != AGVK_None && "Cannot construct AMDGPUMCExpr of kind none.");
// Allocating the variadic arguments through the same allocation mechanism
// that the object itself is allocated with so they end up in the same memory.
@@ -40,25 +38,23 @@ AMDGPUVariadicMCExpr::AMDGPUVariadicMCExpr(VariadicKind Kind,
this->Args = ArrayRef<const MCExpr *>(RawArgs, Args.size());
}
-AMDGPUVariadicMCExpr::~AMDGPUVariadicMCExpr() { Ctx.deallocate(RawArgs); }
+AMDGPUMCExpr::~AMDGPUMCExpr() { Ctx.deallocate(RawArgs); }
-const AMDGPUVariadicMCExpr *
-AMDGPUVariadicMCExpr::create(VariadicKind Kind, ArrayRef<const MCExpr *> Args,
- MCContext &Ctx) {
- return new (Ctx) AMDGPUVariadicMCExpr(Kind, Args, Ctx);
+const AMDGPUMCExpr *AMDGPUMCExpr::create(VariantKind Kind,
+ ArrayRef<const MCExpr *> Args,
+ MCContext &Ctx) {
+ return new (Ctx) AMDGPUMCExpr(Kind, Args, Ctx);
}
-const MCExpr *AMDGPUVariadicMCExpr::getSubExpr(size_t Index) const {
- assert(Index < Args.size() &&
- "Indexing out of bounds AMDGPUVariadicMCExpr sub-expr");
+const MCExpr *AMDGPUMCExpr::getSubExpr(size_t Index) const {
+ assert(Index < Args.size() && "Indexing out of bounds AMDGPUMCExpr sub-expr");
return Args[Index];
}
-void AMDGPUVariadicMCExpr::printImpl(raw_ostream &OS,
- const MCAsmInfo *MAI) const {
+void AMDGPUMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
switch (Kind) {
default:
- llvm_unreachable("Unknown AMDGPUVariadicMCExpr kind.");
+ llvm_unreachable("Unknown AMDGPUMCExpr kind.");
case AGVK_Or:
OS << "or(";
break;
@@ -86,21 +82,19 @@ void AMDGPUVariadicMCExpr::printImpl(raw_ostream &OS,
OS << ')';
}
-static int64_t op(AMDGPUVariadicMCExpr::VariadicKind Kind, int64_t Arg1,
- int64_t Arg2) {
+static int64_t op(AMDGPUMCExpr::VariantKind Kind, int64_t Arg1, int64_t Arg2) {
switch (Kind) {
default:
- llvm_unreachable("Unknown AMDGPUVariadicMCExpr kind.");
- case AMDGPUVariadicMCExpr::AGVK_Max:
+ llvm_unreachable("Unknown AMDGPUMCExpr kind.");
+ case AMDGPUMCExpr::AGVK_Max:
return std::max(Arg1, Arg2);
- case AMDGPUVariadicMCExpr::AGVK_Or:
+ case AMDGPUMCExpr::AGVK_Or:
return Arg1 | Arg2;
}
}
-bool AMDGPUVariadicMCExpr::evaluateExtraSGPRs(MCValue &Res,
- const MCAsmLayout *Layout,
- const MCFixup *Fixup) const {
+bool AMDGPUMCExpr::evaluateExtraSGPRs(MCValue &Res, const MCAsmLayout *Layout,
+ const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
@@ -112,7 +106,7 @@ bool AMDGPUVariadicMCExpr::evaluateExtraSGPRs(MCValue &Res,
};
assert(Args.size() == 3 &&
- "AMDGPUVariadic Argument count incorrect for ExtraSGPRs");
+ "AMDGPUMCExpr Argument count incorrect for ExtraSGPRs");
const MCSubtargetInfo *STI = Ctx.getSubtargetInfo();
uint64_t VCCUsed = 0, FlatScrUsed = 0, XNACKUsed = 0;
@@ -129,9 +123,8 @@ bool AMDGPUVariadicMCExpr::evaluateExtraSGPRs(MCValue &Res,
return true;
}
-bool AMDGPUVariadicMCExpr::evaluateTotalNumVGPR(MCValue &Res,
- const MCAsmLayout *Layout,
- const MCFixup *Fixup) const {
+bool AMDGPUMCExpr::evaluateTotalNumVGPR(MCValue &Res, const MCAsmLayout *Layout,
+ const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
@@ -142,7 +135,7 @@ bool AMDGPUVariadicMCExpr::evaluateTotalNumVGPR(MCValue &Res,
return true;
};
assert(Args.size() == 2 &&
- "AMDGPUVariadic Argument count incorrect for TotalNumVGPRs");
+ "AMDGPUMCExpr Argument count incorrect for TotalNumVGPRs");
const MCSubtargetInfo *STI = Ctx.getSubtargetInfo();
uint64_t NumAGPR = 0, NumVGPR = 0;
@@ -158,9 +151,8 @@ bool AMDGPUVariadicMCExpr::evaluateTotalNumVGPR(MCValue &Res,
return true;
}
-bool AMDGPUVariadicMCExpr::evaluateAlignTo(MCValue &Res,
- const MCAsmLayout *Layout,
- const MCFixup *Fixup) const {
+bool AMDGPUMCExpr::evaluateAlignTo(MCValue &Res, const MCAsmLayout *Layout,
+ const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
@@ -172,7 +164,7 @@ bool AMDGPUVariadicMCExpr::evaluateAlignTo(MCValue &Res,
};
assert(Args.size() == 2 &&
- "AMDGPUVariadic Argument count incorrect for AlignTo");
+ "AMDGPUMCExpr Argument count incorrect for AlignTo");
uint64_t Value = 0, Align = 0;
if (!TryGetMCExprValue(Args[0], Value) || !TryGetMCExprValue(Args[1], Align))
return false;
@@ -181,9 +173,8 @@ bool AMDGPUVariadicMCExpr::evaluateAlignTo(MCValue &Res,
return true;
}
-bool AMDGPUVariadicMCExpr::evaluateOccupancy(MCValue &Res,
- const MCAsmLayout *Layout,
- const MCFixup *Fixup) const {
+bool AMDGPUMCExpr::evaluateOccupancy(MCValue &Res, const MCAsmLayout *Layout,
+ const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
@@ -194,7 +185,7 @@ bool AMDGPUVariadicMCExpr::evaluateOccupancy(MCValue &Res,
return true;
};
assert(Args.size() == 7 &&
- "AMDGPUVariadic Argument count incorrect for Occupancy");
+ "AMDGPUMCExpr Argument count incorrect for Occupancy");
uint64_t InitOccupancy, MaxWaves, Granule, TargetTotalNumVGPRs, Generation,
NumSGPRs, NumVGPRs;
@@ -226,8 +217,9 @@ bool AMDGPUVariadicMCExpr::evaluateOccupancy(MCValue &Res,
return true;
}
-bool AMDGPUVariadicMCExpr::evaluateAsRelocatableImpl(
- MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const {
+bool AMDGPUMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
+ const MCAsmLayout *Layout,
+ const MCFixup *Fixup) const {
std::optional<int64_t> Total;
switch (Kind) {
@@ -258,12 +250,12 @@ bool AMDGPUVariadicMCExpr::evaluateAsRelocatableImpl(
return true;
}
-void AMDGPUVariadicMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
+void AMDGPUMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
for (const MCExpr *Arg : Args)
Streamer.visitUsedExpr(*Arg);
}
-MCFragment *AMDGPUVariadicMCExpr::findAssociatedFragment() const {
+MCFragment *AMDGPUMCExpr::findAssociatedFragment() const {
for (const MCExpr *Arg : Args) {
if (Arg->findAssociatedFragment())
return Arg->findAssociatedFragment();
@@ -275,18 +267,19 @@ MCFragment *AMDGPUVariadicMCExpr::findAssociatedFragment() const {
/// are unresolvable but needed for further MCExprs). Derived from
/// implementation of IsaInfo::getNumExtraSGPRs in AMDGPUBaseInfo.cpp.
///
-const AMDGPUVariadicMCExpr *
-AMDGPUVariadicMCExpr::createExtraSGPRs(const MCExpr *VCCUsed,
- const MCExpr *FlatScrUsed,
- bool XNACKUsed, MCContext &Ctx) {
+const AMDGPUMCExpr *AMDGPUMCExpr::createExtraSGPRs(const MCExpr *VCCUsed,
+ const MCExpr *FlatScrUsed,
+ bool XNACKUsed,
+ MCContext &Ctx) {
return create(AGVK_ExtraSGPRs,
{VCCUsed, FlatScrUsed, MCConstantExpr::create(XNACKUsed, Ctx)},
Ctx);
}
-const AMDGPUVariadicMCExpr *AMDGPUVariadicMCExpr::createTotalNumVGPR(
- const MCExpr *NumAGPR, const MCExpr *NumVGPR, MCContext &Ctx) {
+const AMDGPUMCExpr *AMDGPUMCExpr::createTotalNumVGPR(const MCExpr *NumAGPR,
+ const MCExpr *NumVGPR,
+ MCContext &Ctx) {
return create(AGVK_TotalNumVGPRs, {NumAGPR, NumVGPR}, Ctx);
}
@@ -295,10 +288,11 @@ const AMDGPUVariadicMCExpr *AMDGPUVariadicMCExpr::createTotalNumVGPR(
/// Remove dependency on GCNSubtarget and depend only only the necessary values
/// for said occupancy computation. Should match computeOccupancy implementation
/// without passing \p STM on.
-const AMDGPUVariadicMCExpr *
-AMDGPUVariadicMCExpr::createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
- const MCExpr *NumVGPRs,
- const GCNSubtarget &STM, MCContext &Ctx) {
+const AMDGPUMCExpr *AMDGPUMCExpr::createOccupancy(unsigned InitOcc,
+ const MCExpr *NumSGPRs,
+ const MCExpr *NumVGPRs,
+ const GCNSubtarget &STM,
+ MCContext &Ctx) {
unsigned MaxWaves = IsaInfo::getMaxWavesPerEU(&STM);
unsigned Granule = IsaInfo::getVGPRAllocGranule(&STM);
unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(&STM);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
index f92350b592350..207a619d45a1f 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.h
@@ -17,7 +17,7 @@ namespace llvm {
class Function;
class GCNSubtarget;
-/// AMDGPU target specific variadic MCExpr operations.
+/// AMDGPU target specific MCExpr operations.
///
/// Takes in a minimum of 1 argument to be used with an operation. The supported
/// operations are:
@@ -27,9 +27,9 @@ class GCNSubtarget;
/// \note If the 'or'/'max' operations are provided only a single argument, the
/// operation will act as a no-op and simply resolve as the provided argument.
///
-class AMDGPUVariadicMCExpr : public MCTargetExpr {
+class AMDGPUMCExpr : public MCTargetExpr {
public:
- enum VariadicKind {
+ enum VariantKind {
AGVK_None,
AGVK_Or,
AGVK_Max,
@@ -40,14 +40,13 @@ class AMDGPUVariadicMCExpr : public MCTargetExpr {
};
private:
- VariadicKind Kind;
+ VariantKind Kind;
MCContext &Ctx;
const MCExpr **RawArgs;
ArrayRef<const MCExpr *> Args;
- AMDGPUVariadicMCExpr(VariadicKind Kind, ArrayRef<const MCExpr *> Args,
- MCContext &Ctx);
- ~AMDGPUVariadicMCExpr();
+ AMDGPUMCExpr(VariantKind Kind, ArrayRef<const MCExpr *> Args, MCContext &Ctx);
+ ~AMDGPUMCExpr();
bool evaluateExtraSGPRs(MCValue &Res, const MCAsmLayout *Layout,
const MCFixup *Fixup) const;
@@ -59,40 +58,39 @@ class AMDGPUVariadicMCExpr : public MCTargetExpr {
const MCFixup *Fixup) const;
public:
- static const AMDGPUVariadicMCExpr *
- create(VariadicKind Kind, ArrayRef<const MCExpr *> Args, MCContext &Ctx);
+ static const AMDGPUMCExpr *
+ create(VariantKind Kind, ArrayRef<const MCExpr *> Args, MCContext &Ctx);
- static const AMDGPUVariadicMCExpr *createOr(ArrayRef<const MCExpr *> Args,
- MCContext &Ctx) {
- return create(VariadicKind::AGVK_Or, Args, Ctx);
+ static const AMDGPUMCExpr *createOr(ArrayRef<const MCExpr *> Args,
+ MCContext &Ctx) {
+ return create(VariantKind::AGVK_Or, Args, Ctx);
}
- static const AMDGPUVariadicMCExpr *createMax(ArrayRef<const MCExpr *> Args,
- MCContext &Ctx) {
- return create(VariadicKind::AGVK_Max, Args, Ctx);
+ static const AMDGPUMCExpr *createMax(ArrayRef<const MCExpr *> Args,
+ MCContext &Ctx) {
+ return create(VariantKind::AGVK_Max, Args, Ctx);
}
- static const AMDGPUVariadicMCExpr *createExtraSGPRs(const MCExpr *VCCUsed,
- const MCExpr *FlatScrUsed,
- bool XNACKUsed,
- MCContext &Ctx);
+ static const AMDGPUMCExpr *createExtraSGPRs(const MCExpr *VCCUsed,
+ const MCExpr *FlatScrUsed,
+ bool XNACKUsed, MCContext &Ctx);
- static const AMDGPUVariadicMCExpr *createTotalNumVGPR(const MCExpr *NumAGPR,
- const MCExpr *NumVGPR,
- MCContext &Ctx);
+ static const AMDGPUMCExpr *createTotalNumVGPR(const MCExpr *NumAGPR,
+ const MCExpr *NumVGPR,
+ MCContext &Ctx);
- static const AMDGPUVariadicMCExpr *
+ static const AMDGPUMCExpr *
createAlignTo(const MCExpr *Value, const MCExpr *Align, MCContext &Ctx) {
- return create(VariadicKind::AGVK_AlignTo, {Value, Align}, Ctx);
+ return create(VariantKind::AGVK_AlignTo, {Value, Align}, Ctx);
}
- static const AMDGPUVariadicMCExpr *createOccupancy(unsigned InitOcc,
- const MCExpr *NumSGPRs,
- const MCExpr *NumVGPRs,
- const GCNSubtarget &STM,
- MCContext &Ctx);
+ static const AMDGPUMCExpr *createOccupancy(unsigned InitOcc,
+ const MCExpr *NumSGPRs,
+ const MCExpr *NumVGPRs,
+ const GCNSubtarget &STM,
+ MCContext &Ctx);
- VariadicKind getKind() const { return Kind; }
+ VariantKind getKind() const { return Kind; }
const MCExpr *getSubExpr(size_t Index) const;
void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
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