[llvm] [AArch64] Remove all instances of the 'hasSVEorSME' interfaces. (PR #96543)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 03:16:22 PDT 2024
https://github.com/sdesmalen-arm updated https://github.com/llvm/llvm-project/pull/96543
>From efd1bf08c051649e37832c4f1fd3731701ac9c28 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Fri, 21 Jun 2024 13:18:38 +0100
Subject: [PATCH 1/2] [AArch64] Remove all instances of the 'hasSVEorSME'
interfaces.
I've not added any new tests for these, because the original conditions
were wrong (they did not consider streaming mode) and we have tests
for the positive cases.
---
.../lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 4 +++-
.../lib/Target/AArch64/AArch64ISelLowering.cpp | 18 +++++++++---------
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 3 ++-
llvm/lib/Target/AArch64/AArch64Subtarget.h | 7 ++-----
.../AArch64/AArch64TargetTransformInfo.cpp | 7 ++++---
5 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 248778f98f4c7..5bad1da7da15d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4359,7 +4359,9 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
// N1 = SRL_PRED true, V, splat(imm) --> rotr amount
// N0 = SHL_PRED true, V, splat(bits-imm)
// V = (xor x, y)
- if (VT.isScalableVector() && Subtarget->hasSVE2orSME()) {
+ if (VT.isScalableVector() &&
+ (Subtarget->hasSVE2() ||
+ (Subtarget->hasSME() && Subtarget->isStreaming()))) {
if (N0.getOpcode() != AArch64ISD::SHL_PRED ||
N1.getOpcode() != AArch64ISD::SRL_PRED)
std::swap(N0, N1);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index aa89ff9d9fad1..e0a595899dc46 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1484,7 +1484,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
if (!Subtarget->isLittleEndian())
setOperationAction(ISD::BITCAST, VT, Expand);
- if (Subtarget->hasSVE2orSME())
+ if (Subtarget->hasSVE2() ||
+ (Subtarget->hasSME() && Subtarget->isStreaming()))
// For SLI/SRI.
setOperationAction(ISD::OR, VT, Custom);
}
@@ -1937,7 +1938,7 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
}
bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const {
- if (!Subtarget->hasSVEorSME())
+ if (!Subtarget->isSVEorStreamingSVEAvailable())
return true;
// We can only use the BRKB + CNTP sequence with legal predicate types. We can
@@ -14527,7 +14528,9 @@ SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
Op.getOperand(0), Op.getOperand(1));
case ISD::SRA:
case ISD::SRL:
- if (VT.isScalableVector() && Subtarget->hasSVE2orSME()) {
+ if (VT.isScalableVector() &&
+ (Subtarget->hasSVE2() ||
+ (Subtarget->hasSME() && Subtarget->isStreaming()))) {
SDValue RShOperand;
unsigned ShiftValue;
if (canLowerSRLToRoundingShiftForVT(Op, VT, DAG, ShiftValue, RShOperand))
@@ -16235,14 +16238,11 @@ bool AArch64TargetLowering::isLegalInterleavedAccessType(
UseScalable = false;
if (!VecTy->isScalableTy() && !Subtarget->isNeonAvailable() &&
- !Subtarget->useSVEForFixedLengthVectors())
- return false;
-
- if (VecTy->isScalableTy() && !Subtarget->hasSVEorSME())
+ (!Subtarget->useSVEForFixedLengthVectors() ||
+ !getSVEPredPatternFromNumElements(MinElts)))
return false;
- // Ensure that the predicate for this number of elements is available.
- if (Subtarget->hasSVE() && !getSVEPredPatternFromNumElements(MinElts))
+ if (VecTy->isScalableTy() && !Subtarget->isSVEorStreamingSVEAvailable())
return false;
// Ensure the number of vector elements is greater than 1.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index f972da1e36270..ee397db3fba6d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4675,7 +4675,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (AArch64::FPR128RegClass.contains(DestReg) &&
AArch64::FPR128RegClass.contains(SrcReg)) {
- if (Subtarget.hasSVEorSME() && !Subtarget.isNeonAvailable())
+ if (Subtarget.isSVEorStreamingSVEAvailable() &&
+ !Subtarget.isNeonAvailable())
BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ))
.addReg(AArch64::Z0 + (DestReg - AArch64::Q0), RegState::Define)
.addReg(AArch64::Z0 + (SrcReg - AArch64::Q0))
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 0c9352bda7599..5faba09aa67bd 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -361,20 +361,17 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
void mirFileLoaded(MachineFunction &MF) const override;
- bool hasSVEorSME() const { return hasSVE() || hasSME(); }
- bool hasSVE2orSME() const { return hasSVE2() || hasSME(); }
-
// Return the known range for the bit length of SVE data registers. A value
// of 0 means nothing is known about that particular limit beyong what's
// implied by the architecture.
unsigned getMaxSVEVectorSizeInBits() const {
- assert(hasSVEorSME() &&
+ assert(isSVEorStreamingSVEAvailable() &&
"Tried to get SVE vector length without SVE support!");
return MaxSVEVectorSizeInBits;
}
unsigned getMinSVEVectorSizeInBits() const {
- assert(hasSVEorSME() &&
+ assert(isSVEorStreamingSVEAvailable() &&
"Tried to get SVE vector length without SVE support!");
return MinSVEVectorSizeInBits;
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 632cb23619ddb..368000e0b2a44 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2691,7 +2691,8 @@ InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
return AdjustCost(Entry->Cost);
if ((ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND) &&
- CCH == TTI::CastContextHint::Masked && ST->hasSVEorSME() &&
+ CCH == TTI::CastContextHint::Masked &&
+ ST->isSVEorStreamingSVEAvailable() &&
TLI->getTypeAction(Src->getContext(), SrcTy) ==
TargetLowering::TypePromoteInteger &&
TLI->getTypeAction(Dst->getContext(), DstTy) ==
@@ -2712,8 +2713,8 @@ InstructionCost AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
// The BasicTTIImpl version only deals with CCH==TTI::CastContextHint::Normal,
// but we also want to include the TTI::CastContextHint::Masked case too.
if ((ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND) &&
- CCH == TTI::CastContextHint::Masked && ST->hasSVEorSME() &&
- TLI->isTypeLegal(DstTy))
+ CCH == TTI::CastContextHint::Masked &&
+ ST->isSVEorStreamingSVEAvailable() && TLI->isTypeLegal(DstTy))
CCH = TTI::CastContextHint::Normal;
return AdjustCost(
>From c684358560f41d7d1c6d79d3a0966e1dd2b8ce0e Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 25 Jun 2024 11:15:20 +0100
Subject: [PATCH 2/2] Replace isScalableTy() by isa<ScalableVectorType> (and
isa<FixedVectorType> for the inverse)
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e0a595899dc46..bf38fcc2d2c3b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16237,12 +16237,13 @@ bool AArch64TargetLowering::isLegalInterleavedAccessType(
UseScalable = false;
- if (!VecTy->isScalableTy() && !Subtarget->isNeonAvailable() &&
+ if (isa<FixedVectorType>(VecTy) && !Subtarget->isNeonAvailable() &&
(!Subtarget->useSVEForFixedLengthVectors() ||
!getSVEPredPatternFromNumElements(MinElts)))
return false;
- if (VecTy->isScalableTy() && !Subtarget->isSVEorStreamingSVEAvailable())
+ if (isa<ScalableVectorType>(VecTy) &&
+ !Subtarget->isSVEorStreamingSVEAvailable())
return false;
// Ensure the number of vector elements is greater than 1.
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