[llvm] [AArch64][SVE] optimisation for unary SVE store intrinsics with no active lanes (PR #95793)

[via llvm-commits]

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@@ -1417,6 +1427,10 @@ instCombineSVEST1(InstCombiner &IC, IntrinsicInst &II, const DataLayout &DL) {
   Value *Pred = II.getOperand(1);
   Value *PtrOp = II.getOperand(2);
 
+  // Remove when all lanes are inactive
+  if (auto II_NA = instCombineSVENoActiveUnaryErase(IC, II, 0))
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Lukacma wrote:

You are right this was incorrect. But I also noticed this is unnecessary as other optimizations already optimize this so I removed it altogether

https://github.com/llvm/llvm-project/pull/95793