[llvm] [AMDGPU] Disallow negative s_load offsets in isLegalAddressingMode (PR #91327)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 25 02:21:06 PDT 2024
https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/91327
>From ba9c2c446306082466a001580893089eaee77496 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Tue, 7 May 2024 14:03:54 +0100
Subject: [PATCH 1/3] [AMDGPU] Disallow negative s_load offsets in
isLegalAddressingMode
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 ++++
.../AMDGPU/cgp-addressing-modes-smem.ll | 47 +++++++++----------
2 files changed, 29 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index ed41c10b50d32..dd2dea501380c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1604,6 +1604,14 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
return false;
}
+ if (AS == AMDGPUAS::CONSTANT_ADDRESS && AM.BaseOffs < 0) {
+ // Scalar (non-buffer) loads can only use a negative offset if
+ // soffset+offset is non-negative. Since the compiler can only prove that
+ // in a few special cases, it is safer to claim that negative offsets are
+ // not supported.
+ return false;
+ }
+
if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
return true;
diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
index 54dc5b8b9d3dd..b0bbd90f165b9 100644
--- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
+++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
@@ -279,38 +279,30 @@ end:
}
define amdgpu_cs void @test_sink_smem_offset_neg400(ptr addrspace(4) inreg %ptr, i32 inreg %val) {
-; GFX678-LABEL: test_sink_smem_offset_neg400:
-; GFX678: ; %bb.0: ; %entry
-; GFX678-NEXT: s_add_u32 s0, s0, 0xfffffe70
-; GFX678-NEXT: s_addc_u32 s1, s1, -1
-; GFX678-NEXT: .LBB5_1: ; %loop
-; GFX678-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX678-NEXT: s_waitcnt lgkmcnt(0)
-; GFX678-NEXT: s_load_dword s3, s[0:1], 0x0
-; GFX678-NEXT: s_add_i32 s2, s2, -1
-; GFX678-NEXT: s_cmp_lg_u32 s2, 0
-; GFX678-NEXT: s_cbranch_scc1 .LBB5_1
-; GFX678-NEXT: ; %bb.2: ; %end
-; GFX678-NEXT: s_endpgm
-;
-; GFX9-LABEL: test_sink_smem_offset_neg400:
-; GFX9: ; %bb.0: ; %entry
-; GFX9-NEXT: .LBB5_1: ; %loop
-; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_load_dword s3, s[0:1], -0x190
-; GFX9-NEXT: s_add_i32 s2, s2, -1
-; GFX9-NEXT: s_cmp_lg_u32 s2, 0
-; GFX9-NEXT: s_cbranch_scc1 .LBB5_1
-; GFX9-NEXT: ; %bb.2: ; %end
-; GFX9-NEXT: s_endpgm
+; GFX6789-LABEL: test_sink_smem_offset_neg400:
+; GFX6789: ; %bb.0: ; %entry
+; GFX6789-NEXT: s_add_u32 s0, s0, 0xfffffe70
+; GFX6789-NEXT: s_addc_u32 s1, s1, -1
+; GFX6789-NEXT: .LBB5_1: ; %loop
+; GFX6789-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX6789-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6789-NEXT: s_load_dword s3, s[0:1], 0x0
+; GFX6789-NEXT: s_add_i32 s2, s2, -1
+; GFX6789-NEXT: s_cmp_lg_u32 s2, 0
+; GFX6789-NEXT: s_cbranch_scc1 .LBB5_1
+; GFX6789-NEXT: ; %bb.2: ; %end
+; GFX6789-NEXT: s_endpgm
;
; GFX12-LABEL: test_sink_smem_offset_neg400:
; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_movk_i32 s4, 0xfe70
+; GFX12-NEXT: s_mov_b32 s5, -1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[4:5]
; GFX12-NEXT: .LBB5_1: ; %loop
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_load_b32 s3, s[0:1], -0x190
+; GFX12-NEXT: s_load_b32 s3, s[0:1], 0x0
; GFX12-NEXT: s_add_co_i32 s2, s2, -1
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT: s_cmp_lg_u32 s2, 0
@@ -331,3 +323,6 @@ loop:
end:
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX678: {{.*}}
+; GFX9: {{.*}}
>From e220e1a3eb6f47b9596ae3f9c39c2706cdd7ba1a Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 8 May 2024 15:08:09 +0100
Subject: [PATCH 2/3] Also handle CONSTANT_ADDRESS_32BIT
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index dd2dea501380c..0a10d407fceae 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1604,7 +1604,9 @@ bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
return false;
}
- if (AS == AMDGPUAS::CONSTANT_ADDRESS && AM.BaseOffs < 0) {
+ if ((AS == AMDGPUAS::CONSTANT_ADDRESS ||
+ AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
+ AM.BaseOffs < 0) {
// Scalar (non-buffer) loads can only use a negative offset if
// soffset+offset is non-negative. Since the compiler can only prove that
// in a few special cases, it is safer to claim that negative offsets are
>From 52cd925591d1f6bcdaa63fc1cd854bc3778c19cc Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 8 May 2024 15:49:41 +0100
Subject: [PATCH 3/3] Add test case
---
.../AMDGPU/cgp-addressing-modes-smem.ll | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
index b0bbd90f165b9..c7f7f30a5e6bd 100644
--- a/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
+++ b/llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
@@ -323,6 +323,52 @@ loop:
end:
ret void
}
+
+; Same for address space 6, constant 32-bit.
+define amdgpu_cs void @test_sink_smem_offset_neg400_32bit(ptr addrspace(6) inreg %ptr, i32 inreg %val) {
+; GFX6789-LABEL: test_sink_smem_offset_neg400_32bit:
+; GFX6789: ; %bb.0: ; %entry
+; GFX6789-NEXT: s_add_i32 s2, s0, 0xfffffe70
+; GFX6789-NEXT: s_mov_b32 s3, 0
+; GFX6789-NEXT: .LBB6_1: ; %loop
+; GFX6789-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX6789-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6789-NEXT: s_load_dword s0, s[2:3], 0x0
+; GFX6789-NEXT: s_add_i32 s1, s1, -1
+; GFX6789-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6789-NEXT: s_cbranch_scc1 .LBB6_1
+; GFX6789-NEXT: ; %bb.2: ; %end
+; GFX6789-NEXT: s_endpgm
+;
+; GFX12-LABEL: test_sink_smem_offset_neg400_32bit:
+; GFX12: ; %bb.0: ; %entry
+; GFX12-NEXT: s_add_co_i32 s2, s0, 0xfffffe70
+; GFX12-NEXT: s_mov_b32 s3, 0
+; GFX12-NEXT: .LBB6_1: ; %loop
+; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_load_b32 s0, s[2:3], 0x0
+; GFX12-NEXT: s_add_co_i32 s1, s1, -1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12-NEXT: s_cbranch_scc1 .LBB6_1
+; GFX12-NEXT: ; %bb.2: ; %end
+; GFX12-NEXT: s_endpgm
+entry:
+ %gep = getelementptr i8, ptr addrspace(6) %ptr, i64 -400
+ br label %loop
+
+loop:
+ %count = phi i32 [ %dec, %loop ], [ %val, %entry ]
+ %dec = sub i32 %count, 1
+ %load = load volatile i32, ptr addrspace(6) %gep
+ %cond = icmp eq i32 %dec, 0
+ br i1 %cond, label %end, label %loop
+
+end:
+ ret void
+}
+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX678: {{.*}}
; GFX9: {{.*}}
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