[llvm] [X86][FixupSetCC] Substitute setcc + zext pair with setzucc if possible (PR #96594)

[Shengchen Kan via llvm-commits]

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@@ -98,9 +106,8 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) {
         continue;
 
       // On 32-bit, we need to be careful to force an ABCD register.
-      const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
-                                          ? &X86::GR32RegClass
-                                          : &X86::GR32_ABCDRegClass;
+      const TargetRegisterClass *RC =
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KanRobert wrote:

It's kind of related.  There are 2 uses of `X86Subtarget` after this PR, so I define the variable `ST` for it.  Unless we'd like to define the variable even for 1 use,  I can not extract this into a separate NFC change.

https://github.com/llvm/llvm-project/pull/96594