[llvm] [RISCV] Let LiveIntervals::shrinkToUses compute dead AVLs (PR #90629)

Luke Lau via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 24 23:17:35 PDT 2024


https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/90629

>From e4481995881a3c08d54f7eccbfe828a6b5d01fda Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 1 May 2024 01:19:56 +0800
Subject: [PATCH] [RISCV] Let LiveIntervals::shrinkToUses compute dead
 immediate. NFC

We can simplify removing dead AVL immediates > 31 by using the dead argument to shrinkToUses, since it will already compute dead values.
---
 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp  | 30 ++++++++++---------
 .../test/CodeGen/RISCV/rvv/vsetvli-insert.mir |  3 +-
 2 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 101f188374e0c..23e4096b9a721 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1696,19 +1696,10 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
           if (NextMI->getOperand(1).isReg())
             NextMI->getOperand(1).setReg(RISCV::NoRegister);
 
-          if (OldVLReg && OldVLReg.isVirtual()) {
-            // NextMI no longer uses OldVLReg so shrink its LiveInterval.
-            if (LIS)
-              LIS->shrinkToUses(&LIS->getInterval(OldVLReg));
-
-            MachineInstr *VLOpDef = MRI->getUniqueVRegDef(OldVLReg);
-            if (VLOpDef && TII->isAddImmediate(*VLOpDef, OldVLReg) &&
-                MRI->use_nodbg_empty(OldVLReg)) {
-              VLOpDef->eraseFromParent();
-              if (LIS)
-                LIS->removeInterval(OldVLReg);
-            }
-          }
+          // NextMI no longer uses OldVLReg so shrink its LiveInterval.
+          if (OldVLReg && OldVLReg.isVirtual() && LIS)
+            LIS->shrinkToUses(&LIS->getInterval(OldVLReg), &ToDelete);
+
           MI.setDesc(NextMI->getDesc());
         }
         MI.getOperand(2).setImm(NextMI->getOperand(2).getImm());
@@ -1720,11 +1711,22 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
     Used = getDemanded(MI, ST);
   }
 
-  NumCoalescedVSETVL += ToDelete.size();
   for (auto *MI : ToDelete) {
+    bool SawStore = false;
+    if (!MI->isSafeToMove(nullptr, SawStore) || MI->isBundled() ||
+        MI->isInlineAsm()) {
+      assert(!isVectorConfigInstr(*MI));
+      continue;
+    }
+
     if (LIS)
       LIS->RemoveMachineInstrFromMaps(*MI);
     MI->eraseFromParent();
+    if (LIS)
+      for (MachineOperand &MO : MI->uses())
+        if (MO.isReg() && MO.getReg().isVirtual())
+          LIS->shrinkToUses(&LIS->getInterval(MO.getReg()));
+    NumCoalescedVSETVL++;
   }
 }
 
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 681b50de5b81c..ba4472aefa8db 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -539,8 +539,7 @@ body:             |
     ; CHECK-LABEL: name: coalesce_dead_avl_nonvolatile_load
     ; CHECK: liveins: $x1
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: %ptr:gpr = COPY $x1
-    ; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (dereferenceable load (s32))
+    ; CHECK-NEXT: dead %ptr:gpr = COPY $x1
     ; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
     ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype
     ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype



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