[llvm] [LSV] Enhance LoadStoreVectorizer to Handle Disjoint Flag in OR Instructions and Restore Vectorization Opportunities (PR #96495)

[Hao Li via llvm-commits]

LiHao217 wrote:

> This needs a phase ordering test to demonstrate why the disjoint flag is not present at the point where LSV runs. Then we can either try to make sure the flag is present at that point, or make SCEV fall back to haveNoCommonBitsSet() -- I don't think that we want to infer it in LSV specifically.
@nikic 
Hi nikic,
I have provided a phase ordering test case that clearly demonstrates the scenario where the disjoint flag is missing when the LoadStoreVectorizer (LSV) runs. You can find the test case here:
[LLVM/test/Transforms/LoadStoreVectorizer/NVPTX/disjoint_or_vectorizer.ll](https://github.com/llvm/llvm-project/blob/ece0efcb68ac0868d128b70b92b83a5b1801b62e/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/disjoint_or_vectorizer.ll)

You can run the test with the following command:
`opt -mtriple=nvptx64-nvidia-cuda -debug-pass-manager -passes=load-store-vectorizer -S -o - llvm/test/Transforms/LoadStoreVectorizer/NVPTX/disjoint_or_vectorizer.ll`

This test case demonstrates the issue with the missing disjoint flag when LSV runs, which helps in understanding why the disjoint flag is not being properly propagated through the prior optimization phases.

Could you please advise on the appropriate phase or location to set the disjoint flag? I am willing to make the necessary modifications based on your guidance.

Thank you for your help!

Best regards,
LiHao217


https://github.com/llvm/llvm-project/pull/96495