[llvm] [RISCV] Add FPR16 regbank and start legalizing f16 operations for Zfh. (PR #96582)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 24 22:25:33 PDT 2024
================
@@ -0,0 +1,194 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fadd_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fadd_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FADD_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FADD %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsub_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fsub_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FSUB_H:%[0-9]+]]:fpr16 = nofpexcept FSUB_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FSUB_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FSUB %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fmul_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fmul_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FMUL_H:%[0-9]+]]:fpr16 = nofpexcept FMUL_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FMUL_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FMUL %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fdiv_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fdiv_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FDIV_H:%[0-9]+]]:fpr16 = nofpexcept FDIV_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FDIV_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FDIV %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fma_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fma_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $f12_h
+ ; CHECK-NEXT: [[FMADD_H:%[0-9]+]]:fpr16 = nofpexcept FMADD_H [[COPY]], [[COPY1]], [[COPY2]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FMADD_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = COPY $f12_h
+ %3:fprb(s16) = G_FMA %0, %1, %2
+ $f10_h = COPY %3(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fneg_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fneg_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FSGNJN_H:%[0-9]+]]:fpr16 = FSGNJN_H [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSGNJN_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = G_FNEG %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fabs_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fabs_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FSGNJX_H:%[0-9]+]]:fpr16 = FSGNJX_H [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSGNJX_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = G_FABS %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsqrt_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fsqrt_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FSQRT_H:%[0-9]+]]:fpr16 = nofpexcept FSQRT_H [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FSQRT_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = G_FSQRT %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
----------------
topperc wrote:
Oops. I naively assumed that all the f32 tests were together when I copied this over.
https://github.com/llvm/llvm-project/pull/96582
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