[llvm] [RISCV] Add FPR16 regbank and start legalizing f16 operations for Zfh. (PR #96582)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 24 18:54:07 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/96582
None
>From b0cbc8a5e29c5349127e9b4ef9c132c8d5f8f509 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 24 Jun 2024 18:41:41 -0700
Subject: [PATCH] [RISCV] Add FPR16 regbank and start legalizing f16 operations
for Zfh.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 18 +-
.../RISCV/GISel/RISCVRegisterBankInfo.cpp | 47 +++-
.../instruction-select/fp-arith-f16.mir | 194 +++++++++++++
.../legalizer/legalize-fp-arith-f16.mir | 233 ++++++++++++++++
.../GlobalISel/regbankselect/fp-arith-f16.mir | 257 ++++++++++++++++++
5 files changed, 730 insertions(+), 19 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index e003b6b8ee4e1..bec542f7781b1 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -371,17 +371,25 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
// FP Operations
- getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FNEG,
- G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM})
- .legalIf(typeIsScalarFPArith(0, ST));
+ auto &FPArithActions = getActionDefinitionsBuilder(
+ {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FNEG,
+ G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM})
+ .legalIf(typeIsScalarFPArith(0, ST));
+ // TODO: Fold this into typeIsScalarFPArith.
+ if (ST.hasStdExtZfh())
+ FPArithActions.legalFor({s16});
getActionDefinitionsBuilder(G_FREM)
.libcallFor({s32, s64})
.minScalar(0, s32)
.scalarize(0);
- getActionDefinitionsBuilder(G_FCOPYSIGN)
- .legalIf(all(typeIsScalarFPArith(0, ST), typeIsScalarFPArith(1, ST)));
+ auto &CopySignActions =
+ getActionDefinitionsBuilder(G_FCOPYSIGN)
+ .legalIf(all(typeIsScalarFPArith(0, ST), typeIsScalarFPArith(1, ST)));
+ // TODO: Fold this into typeIsScalarFPArith.
+ if (ST.hasStdExtZfh())
+ CopySignActions.legalFor({s16, s16});
getActionDefinitionsBuilder(G_FPTRUNC).legalIf(
[=, &ST](const LegalityQuery &Query) -> bool {
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 686c8d89a7321..41ca164b38f3d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -29,6 +29,7 @@ const RegisterBankInfo::PartialMapping PartMappings[] = {
// clang-format off
{0, 32, GPRBRegBank},
{0, 64, GPRBRegBank},
+ {0, 16, FPRBRegBank},
{0, 32, FPRBRegBank},
{0, 64, FPRBRegBank},
{0, 64, VRBRegBank},
@@ -41,12 +42,13 @@ const RegisterBankInfo::PartialMapping PartMappings[] = {
enum PartialMappingIdx {
PMI_GPRB32 = 0,
PMI_GPRB64 = 1,
- PMI_FPRB32 = 2,
- PMI_FPRB64 = 3,
- PMI_VRB64 = 4,
- PMI_VRB128 = 5,
- PMI_VRB256 = 6,
- PMI_VRB512 = 7,
+ PMI_FPRB16 = 2,
+ PMI_FPRB32 = 3,
+ PMI_FPRB64 = 4,
+ PMI_VRB64 = 5,
+ PMI_VRB128 = 6,
+ PMI_VRB256 = 7,
+ PMI_VRB512 = 8,
};
const RegisterBankInfo::ValueMapping ValueMappings[] = {
@@ -60,6 +62,10 @@ const RegisterBankInfo::ValueMapping ValueMappings[] = {
{&PartMappings[PMI_GPRB64], 1},
{&PartMappings[PMI_GPRB64], 1},
{&PartMappings[PMI_GPRB64], 1},
+ // Maximum 3 FPR operands; 16 bit.
+ {&PartMappings[PMI_FPRB16], 1},
+ {&PartMappings[PMI_FPRB16], 1},
+ {&PartMappings[PMI_FPRB16], 1},
// Maximum 3 FPR operands; 32 bit.
{&PartMappings[PMI_FPRB32], 1},
{&PartMappings[PMI_FPRB32], 1},
@@ -90,12 +96,13 @@ enum ValueMappingIdx {
InvalidIdx = 0,
GPRB32Idx = 1,
GPRB64Idx = 4,
- FPRB32Idx = 7,
- FPRB64Idx = 10,
- VRB64Idx = 13,
- VRB128Idx = 16,
- VRB256Idx = 19,
- VRB512Idx = 22,
+ FPRB16Idx = 7,
+ FPRB32Idx = 10,
+ FPRB64Idx = 13,
+ VRB64Idx = 16,
+ VRB128Idx = 19,
+ VRB256Idx = 22,
+ VRB512Idx = 25,
};
} // namespace RISCV
} // namespace llvm
@@ -151,8 +158,20 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
}
static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
- assert(Size == 32 || Size == 64);
- unsigned Idx = Size == 64 ? RISCV::FPRB64Idx : RISCV::FPRB32Idx;
+ unsigned Idx;
+ switch (Size) {
+ default:
+ llvm_unreachable("Unexpected size");
+ case 16:
+ Idx = RISCV::FPRB16Idx;
+ break;
+ case 32:
+ Idx = RISCV::FPRB32Idx;
+ break;
+ case 64:
+ Idx = RISCV::FPRB64Idx;
+ break;
+ }
return &RISCV::ValueMappings[Idx];
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
new file mode 100644
index 0000000000000..449e45467728d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-arith-f16.mir
@@ -0,0 +1,194 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=instruction-select \
+# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: fadd_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fadd_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FADD_H:%[0-9]+]]:fpr16 = nofpexcept FADD_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FADD_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FADD %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsub_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fsub_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FSUB_H:%[0-9]+]]:fpr16 = nofpexcept FSUB_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FSUB_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FSUB %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fmul_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fmul_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FMUL_H:%[0-9]+]]:fpr16 = nofpexcept FMUL_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FMUL_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FMUL %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fdiv_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fdiv_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[FDIV_H:%[0-9]+]]:fpr16 = nofpexcept FDIV_H [[COPY]], [[COPY1]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FDIV_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = G_FDIV %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fma_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fma_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY $f11_h
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY $f12_h
+ ; CHECK-NEXT: [[FMADD_H:%[0-9]+]]:fpr16 = nofpexcept FMADD_H [[COPY]], [[COPY1]], [[COPY2]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FMADD_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = COPY $f11_h
+ %2:fprb(s16) = COPY $f12_h
+ %3:fprb(s16) = G_FMA %0, %1, %2
+ $f10_h = COPY %3(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fneg_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fneg_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FSGNJN_H:%[0-9]+]]:fpr16 = FSGNJN_H [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSGNJN_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = G_FNEG %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fabs_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fabs_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FSGNJX_H:%[0-9]+]]:fpr16 = FSGNJX_H [[COPY]], [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSGNJX_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = G_FABS %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsqrt_f16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fsqrt_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
+ ; CHECK-NEXT: [[FSQRT_H:%[0-9]+]]:fpr16 = nofpexcept FSQRT_H [[COPY]], 7
+ ; CHECK-NEXT: $f10_h = COPY [[FSQRT_H]]
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:fprb(s16) = COPY $f10_h
+ %1:fprb(s16) = G_FSQRT %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
new file mode 100644
index 0000000000000..f1777e945b12d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-arith-f16.mir
@@ -0,0 +1,233 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+
+---
+name: fadd_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fadd_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s16) = G_FADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FADD %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsub_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fsub_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s16) = G_FSUB [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSUB]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FSUB %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fmul_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fmul_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s16) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMUL]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FMUL %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fdiv_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fdiv_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s16) = G_FDIV [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FDIV]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FDIV %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fma_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fma_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s16) = COPY $f12_h
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s16) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMA]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = COPY $f12_h
+ %3:_(s16) = G_FMA %0, %1, %2
+ $f10_h = COPY %3(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fneg_f16
+body: |
+ bb.0:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fneg_f16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FNEG]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FNEG %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fabs_f16
+body: |
+ bb.0:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fabs_f16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s16) = G_FABS [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FABS]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FABS %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsqrt_f16
+body: |
+ bb.0:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fsqrt_f16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:_(s16) = G_FSQRT [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSQRT]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FSQRT %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fmaxnum_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fmaxnum_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s16) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMAXNUM]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FMAXNUM %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fminnum_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fminnum_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s16) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMINNUM]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FMINNUM %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fcopysign_f16
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcopysign_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:_(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
+ ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FCOPYSIGN %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
new file mode 100644
index 0000000000000..ace4aa542377b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith-f16.mir
@@ -0,0 +1,257 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+# RUN: llc -mtriple=riscv64 -mattr=+zfh -run-pass=regbankselect \
+# RUN: -simplify-mir -verify-machineinstrs %s \
+# RUN: -o - | FileCheck %s
+
+---
+name: fadd_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fadd_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s16) = G_FADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FADD]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FADD %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsub_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fsub_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s16) = G_FSUB [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSUB]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FSUB %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fmul_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fmul_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s16) = G_FMUL [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMUL]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FMUL %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fdiv_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fdiv_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s16) = G_FDIV [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FDIV]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FDIV %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fma_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h, $f12_h
+
+ ; CHECK-LABEL: name: fma_f16
+ ; CHECK: liveins: $f10_h, $f11_h, $f12_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fprb(s16) = COPY $f12_h
+ ; CHECK-NEXT: [[FMA:%[0-9]+]]:fprb(s16) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMA]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = COPY $f12_h
+ %3:_(s16) = G_FMA %0, %1, %2
+ $f10_h = COPY %3(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fneg_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fneg_f16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FNEG:%[0-9]+]]:fprb(s16) = G_FNEG [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FNEG]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FNEG %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fabs_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fabs_f16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FABS:%[0-9]+]]:fprb(s16) = G_FABS [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FABS]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FABS %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fsqrt_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h
+
+ ; CHECK-LABEL: name: fsqrt_f16
+ ; CHECK: liveins: $f10_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[FSQRT:%[0-9]+]]:fprb(s16) = G_FSQRT [[COPY]]
+ ; CHECK-NEXT: $f10_h = COPY [[FSQRT]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = G_FSQRT %0
+ $f10_h = COPY %1(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fmaxnum_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fmaxnum_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:fprb(s16) = G_FMAXNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMAXNUM]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FMAXNUM %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fminnum_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fminnum_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:fprb(s16) = G_FMINNUM [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $f10_h = COPY [[FMINNUM]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FMINNUM %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
+---
+name: fcopysign_f16
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $f10_h, $f11_h
+
+ ; CHECK-LABEL: name: fcopysign_f16
+ ; CHECK: liveins: $f10_h, $f11_h
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s16) = COPY $f10_h
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s16) = COPY $f11_h
+ ; CHECK-NEXT: [[FCOPYSIGN:%[0-9]+]]:fprb(s16) = G_FCOPYSIGN [[COPY]], [[COPY1]](s16)
+ ; CHECK-NEXT: $f10_h = COPY [[FCOPYSIGN]](s16)
+ ; CHECK-NEXT: PseudoRET implicit $f10_h
+ %0:_(s16) = COPY $f10_h
+ %1:_(s16) = COPY $f11_h
+ %2:_(s16) = G_FCOPYSIGN %0, %1
+ $f10_h = COPY %2(s16)
+ PseudoRET implicit $f10_h
+
+...
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