[llvm] [RISCV] Relax RISCVInsertVSETVLI output VL peeking to cover registers (PR #96200)

[Craig Topper via llvm-commits]

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@@ -328,7 +328,8 @@ define <vscale x 1 x double> @test8(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
 ; CHECK-NEXT:    csrr a2, vlenb
 ; CHECK-NEXT:    slli a2, a2, 1
 ; CHECK-NEXT:    sub sp, sp, a2
-; CHECK-NEXT:    vsetvli s0, a0, e64, m1, ta, ma
+; CHECK-NEXT:    mv s0, a0
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
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topperc wrote:

in-order cores can't really implement mv elimination since it requires register renaming.

https://github.com/llvm/llvm-project/pull/96200