[llvm] [ValueTypes] Add v1 to v12 vector type support for i1, i8, i16, f16, … (PR #96481)

Kito Cheng via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 24 07:15:56 PDT 2024 

================
@@ -237,8 +237,22 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
     return FixedVectorType::get(Type::getInt1Ty(Context), 3);
   case MVT::v4i1:
     return FixedVectorType::get(Type::getInt1Ty(Context), 4);
+  case MVT::v5i1:
+    return FixedVectorType::get(Type::getInt1Ty(Context), 5);
+  case MVT::v6i1:
+    return FixedVectorType::get(Type::getInt1Ty(Context), 6);
+  case MVT::v7i1:
+    return FixedVectorType::get(Type::getInt1Ty(Context), 7);
----------------
kito-cheng wrote:

Got 227 failed test from various targets if we don't add new MVT to this function..., most fails are come from `llvm::SelectionDAGISel::LowerArguments ->VT.getTypeForEVT`[1]

[1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp#L11365
```
Failed Tests (227):
  LLVM :: CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  LLVM :: CodeGen/AArch64/GlobalISel/translate-sve-formal-argument.ll
  LLVM :: CodeGen/AArch64/aarch64-bf16-ldst-intrinsics.ll
  LLVM :: CodeGen/AArch64/aarch64-interleaved-ld-combine.ll
  LLVM :: CodeGen/AArch64/abs.ll
  LLVM :: CodeGen/AArch64/arm64-copy-tuple.ll
  LLVM :: CodeGen/AArch64/arm64-indexed-vector-ldst.ll
  LLVM :: CodeGen/AArch64/arm64-ld1.ll
  LLVM :: CodeGen/AArch64/arm64-neon-vector-list-spill.ll
  LLVM :: CodeGen/AArch64/arm64-st1.ll
  LLVM :: CodeGen/AArch64/bitcast.ll
  LLVM :: CodeGen/AArch64/bswap.ll
  LLVM :: CodeGen/AArch64/cmp-select-sign.ll
  LLVM :: CodeGen/AArch64/fabs.ll
  LLVM :: CodeGen/AArch64/faddsub.ll
  LLVM :: CodeGen/AArch64/fcmp.ll
  LLVM :: CodeGen/AArch64/fcopysign.ll
  LLVM :: CodeGen/AArch64/fcvt.ll
  LLVM :: CodeGen/AArch64/fdiv.ll
  LLVM :: CodeGen/AArch64/fexplog.ll
  LLVM :: CodeGen/AArch64/fminimummaximum.ll
  LLVM :: CodeGen/AArch64/fminmax.ll
  LLVM :: CodeGen/AArch64/fmla.ll
  LLVM :: CodeGen/AArch64/fmul.ll
  LLVM :: CodeGen/AArch64/fneg.ll
  LLVM :: CodeGen/AArch64/fp16-vector-load-store.ll
  LLVM :: CodeGen/AArch64/fpow.ll
  LLVM :: CodeGen/AArch64/fpowi.ll
  LLVM :: CodeGen/AArch64/fptosi-sat-vector.ll
  LLVM :: CodeGen/AArch64/fptoui-sat-vector.ll
  LLVM :: CodeGen/AArch64/frem.ll
  LLVM :: CodeGen/AArch64/fsincos.ll
  LLVM :: CodeGen/AArch64/fsqrt.ll
  LLVM :: CodeGen/AArch64/load.ll
  LLVM :: CodeGen/AArch64/multi-vector-store-size.ll
  LLVM :: CodeGen/AArch64/neon-dotreduce.ll
  LLVM :: CodeGen/AArch64/nontemporal-load.ll
  LLVM :: CodeGen/AArch64/sadd_sat_vec.ll
  LLVM :: CodeGen/AArch64/shift.ll
  LLVM :: CodeGen/AArch64/shufflevector.ll
  LLVM :: CodeGen/AArch64/ssub_sat_vec.ll
  LLVM :: CodeGen/AArch64/store.ll
  LLVM :: CodeGen/AArch64/sve-fixed-length-function-calls.ll
  LLVM :: CodeGen/AArch64/sve-fixed-length-functions.ll
  LLVM :: CodeGen/AArch64/sve-llrint.ll
  LLVM :: CodeGen/AArch64/sve-lrint.ll
  LLVM :: CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
  LLVM :: CodeGen/AArch64/tbl-loops.ll
  LLVM :: CodeGen/AArch64/trunc-to-tbl.ll
  LLVM :: CodeGen/AArch64/uadd_sat_vec.ll
  LLVM :: CodeGen/AArch64/usub_sat_vec.ll
  LLVM :: CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
  LLVM :: CodeGen/AArch64/vecreduce-add-legalization.ll
  LLVM :: CodeGen/AArch64/vecreduce-and-legalization.ll
  LLVM :: CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll
  LLVM :: CodeGen/AArch64/vecreduce-fmax-legalization.ll
  LLVM :: CodeGen/AArch64/vecreduce-fmaximum.ll
  LLVM :: CodeGen/AArch64/vecreduce-fmin-legalization.ll
  LLVM :: CodeGen/AArch64/vecreduce-fminimum.ll
  LLVM :: CodeGen/AArch64/vecreduce-umax-legalization.ll
  LLVM :: CodeGen/AArch64/vldn_shuffle.ll
  LLVM :: CodeGen/AArch64/vselect-ext.ll
  LLVM :: CodeGen/AArch64/zext-to-tbl.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/add.vni16.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/extractelement.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/function-returns.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/insertelement.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/saddsat.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/ssubsat.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/uaddsat.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/usubsat.ll
  LLVM :: CodeGen/AMDGPU/abs_i16.ll
  LLVM :: CodeGen/AMDGPU/amdgcn.bitcast.ll
  LLVM :: CodeGen/AMDGPU/calling-conventions.ll
  LLVM :: CodeGen/AMDGPU/copy-hoist-no-spills.ll
  LLVM :: CodeGen/AMDGPU/copy-illegal-type.ll
  LLVM :: CodeGen/AMDGPU/copy-to-reg-scc-clobber.ll
  LLVM :: CodeGen/AMDGPU/cvt_f32_ubyte.ll
  LLVM :: CodeGen/AMDGPU/fcanonicalize.f16.ll
  LLVM :: CodeGen/AMDGPU/flat_atomics_i64.ll
  LLVM :: CodeGen/AMDGPU/function-args-inreg.ll
  LLVM :: CodeGen/AMDGPU/function-args.ll
  LLVM :: CodeGen/AMDGPU/function-returns.ll
  LLVM :: CodeGen/AMDGPU/gfx-callable-argument-types.ll
  LLVM :: CodeGen/AMDGPU/global-i16-load-store.ll
  LLVM :: CodeGen/AMDGPU/global-saddr-load.ll
  LLVM :: CodeGen/AMDGPU/global-saddr-store.ll
  LLVM :: CodeGen/AMDGPU/global_atomics_i64.ll
  LLVM :: CodeGen/AMDGPU/idot4s.ll
  LLVM :: CodeGen/AMDGPU/idot4u.ll
  LLVM :: CodeGen/AMDGPU/insert_vector_dynelt.ll
  LLVM :: CodeGen/AMDGPU/kernel-args.ll
  LLVM :: CodeGen/AMDGPU/llvm.is.fpclass.ll
  LLVM :: CodeGen/AMDGPU/permute_i8.ll
  LLVM :: CodeGen/AMDGPU/preload-kernargs.ll
  LLVM :: CodeGen/AMDGPU/select.f16.ll
  LLVM :: CodeGen/AMDGPU/selectcc.ll
  LLVM :: CodeGen/AMDGPU/v_mac_f16.ll
  LLVM :: CodeGen/AMDGPU/v_madak_f16.ll
  LLVM :: CodeGen/AMDGPU/vector_rebroadcast.ll
  LLVM :: CodeGen/AMDGPU/vector_shuffle.packed.ll
  LLVM :: CodeGen/AMDGPU/vni8-across-blocks.ll
  LLVM :: CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
  LLVM :: CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
  LLVM :: CodeGen/ARM/arm-insert-subvector.ll
  LLVM :: CodeGen/ARM/arm-vld1.ll
  LLVM :: CodeGen/ARM/arm-vlddup-update.ll
  LLVM :: CodeGen/ARM/arm-vlddup.ll
  LLVM :: CodeGen/ARM/arm-vst1.ll
  LLVM :: CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
  LLVM :: CodeGen/ARM/bf16-intrinsics-ld-st.ll
  LLVM :: CodeGen/ARM/legalize-bitcast.ll
  LLVM :: CodeGen/ARM/vld3.ll
  LLVM :: CodeGen/ARM/vldlane.ll
  LLVM :: CodeGen/ARM/vst3.ll
  LLVM :: CodeGen/ARM/vstlane.ll
  LLVM :: CodeGen/ARM/vuzp.ll
  LLVM :: CodeGen/Hexagon/autohvx/isel-hvx-concat-truncate.ll
  LLVM :: CodeGen/Hexagon/autohvx/isel-undef-not-zero.ll
  LLVM :: CodeGen/NVPTX/param-load-store.ll
  LLVM :: CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll
  LLVM :: CodeGen/PowerPC/build-vector-to-ld-chain.ll
  LLVM :: CodeGen/PowerPC/git_revision.ll
  LLVM :: CodeGen/PowerPC/vec-zext-abdu.ll
  LLVM :: CodeGen/RISCV/rvv/ceil-vp.ll
  LLVM :: CodeGen/RISCV/rvv/extractelt-fp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-abs.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-int.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-load.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-store.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  LLVM :: CodeGen/RISCV/rvv/floor-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fmaximum-vp.ll
  LLVM :: CodeGen/RISCV/rvv/fminimum-vp.ll
  LLVM :: CodeGen/RISCV/rvv/nearbyint-vp.ll
  LLVM :: CodeGen/RISCV/rvv/rint-vp.ll
  LLVM :: CodeGen/RISCV/rvv/round-vp.ll
  LLVM :: CodeGen/RISCV/rvv/roundeven-vp.ll
  LLVM :: CodeGen/RISCV/rvv/roundtozero-vp.ll
  LLVM :: CodeGen/RISCV/rvv/setcc-fp.ll
  LLVM :: CodeGen/RISCV/rvv/strided-vpstore.ll
  LLVM :: CodeGen/RISCV/rvv/vector-deinterleave.ll
  LLVM :: CodeGen/RISCV/rvv/vfabs-vp.ll
  LLVM :: CodeGen/RISCV/rvv/vfma-vp.ll
  LLVM :: CodeGen/RISCV/rvv/vfmuladd-vp.ll
  LLVM :: CodeGen/RISCV/rvv/vfneg-vp.ll
  LLVM :: CodeGen/RISCV/rvv/vfptrunc-vp.ll
  LLVM :: CodeGen/RISCV/rvv/vfsqrt-vp.ll
  LLVM :: CodeGen/RISCV/rvv/vpload.ll
  LLVM :: CodeGen/RISCV/rvv/vpscatter-sdnode.ll
  LLVM :: CodeGen/RISCV/rvv/vpstore.ll
  LLVM :: CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
  LLVM :: CodeGen/RISCV/rvv/vselect-fp.ll
  LLVM :: CodeGen/RISCV/rvv/vselect-vp.ll
  LLVM :: CodeGen/SystemZ/vec-move-23.ll
  LLVM :: CodeGen/Thumb2/mve-fptosi-sat-vector.ll
  LLVM :: CodeGen/Thumb2/mve-fptoui-sat-vector.ll
  LLVM :: CodeGen/Thumb2/mve-vld3.ll
  LLVM :: CodeGen/WebAssembly/simd-bitmask.ll
  LLVM :: CodeGen/WebAssembly/simd-vecreduce-bool.ll
  LLVM :: CodeGen/X86/avx512-calling-conv.ll
  LLVM :: CodeGen/X86/i64-mem-copy.ll
  LLVM :: CodeGen/X86/matrix-multiply.ll
  LLVM :: CodeGen/X86/mem-promote-integers.ll
  LLVM :: CodeGen/X86/oddshuffles.ll
  LLVM :: CodeGen/X86/oddsubvector.ll
  LLVM :: CodeGen/X86/pr44976.ll
  LLVM :: CodeGen/X86/pr45563-2.ll
  LLVM :: CodeGen/X86/pr45833.ll
  LLVM :: CodeGen/X86/pr50709.ll
  LLVM :: CodeGen/X86/sadd_sat_vec.ll
  LLVM :: CodeGen/X86/scalar_widen_div.ll
  LLVM :: CodeGen/X86/shrink_vmul.ll
  LLVM :: CodeGen/X86/ssub_sat_vec.ll
  LLVM :: CodeGen/X86/subvectorwise-store-of-vector-splat.ll
  LLVM :: CodeGen/X86/uadd_sat_vec.ll
  LLVM :: CodeGen/X86/usub_sat_vec.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
  LLVM :: CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
  LLVM :: CodeGen/X86/vector-intrinsics.ll
  LLVM :: CodeGen/X86/widen_arith-4.ll
  LLVM :: CodeGen/X86/widen_conv-1.ll
  LLVM :: CodeGen/X86/widen_conv-4.ll
  LLVM :: CodeGen/X86/widen_load-2.ll
  LLVM :: CodeGen/X86/widen_load-3.ll


Testing Time: 787.42s

Total Discovered Tests: 100958
  Skipped          :    19 (0.02%)
  Unsupported      :  1174 (1.16%)
  Passed           : 99342 (98.40%)
  Expectedly Failed:   196 (0.19%)
  Failed           :   227 (0.22%)
```

https://github.com/llvm/llvm-project/pull/96481

More information about the llvm-commits mailing list