[llvm] [ValueTypes] Add v1 to v12 vector type support for i1, i8, i16, f16, … (PR #96481)

[Kito Cheng via llvm-commits]

================
@@ -57,61 +57,61 @@ define void @load_i64_stride5_vf2(ptr %in.vec, ptr %out.vec0, ptr %out.vec1, ptr
 ;
 ; AVX2-LABEL: load_i64_stride5_vf2:
 ; AVX2:       # %bb.0:
-; AVX2-NEXT:    vmovaps (%rdi), %ymm0
-; AVX2-NEXT:    vmovdqa (%rdi), %xmm1
-; AVX2-NEXT:    vmovdqa 32(%rdi), %xmm2
-; AVX2-NEXT:    vmovdqa 48(%rdi), %xmm3
-; AVX2-NEXT:    vmovdqa 64(%rdi), %xmm4
-; AVX2-NEXT:    vpblendd {{.*#+}} xmm5 = xmm1[0,1],xmm2[2,3]
-; AVX2-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7]
-; AVX2-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],mem[2,3],ymm0[4,5],mem[6,7]
-; AVX2-NEXT:    vpalignr {{.*#+}} xmm3 = mem[8,9,10,11,12,13,14,15],xmm4[0,1,2,3,4,5,6,7]
-; AVX2-NEXT:    vpblendd {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3]
-; AVX2-NEXT:    vmovdqa %xmm5, (%rsi)
-; AVX2-NEXT:    vmovdqa %xmm1, (%rdx)
-; AVX2-NEXT:    vextractf128 $1, %ymm0, (%rcx)
-; AVX2-NEXT:    vmovdqa %xmm3, (%r8)
-; AVX2-NEXT:    vmovdqa %xmm2, (%r9)
+; AVX2-NEXT:    vmovdqa (%rdi), %xmm0
+; AVX2-NEXT:    vmovdqa 32(%rdi), %xmm1
+; AVX2-NEXT:    vmovdqa 48(%rdi), %xmm2
+; AVX2-NEXT:    vmovdqa 64(%rdi), %xmm3
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm4 = xmm0[0,1],xmm1[2,3]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4,5,6,7]
+; AVX2-NEXT:    vmovaps (%rdi), %ymm2
+; AVX2-NEXT:    vblendps {{.*#+}} ymm2 = ymm2[0,1],mem[2,3],ymm2[4,5],mem[6,7]
+; AVX2-NEXT:    vpalignr {{.*#+}} xmm5 = mem[8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7]
+; AVX2-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3]
+; AVX2-NEXT:    vmovdqa %xmm4, (%rsi)
+; AVX2-NEXT:    vmovdqa %xmm0, (%rdx)
+; AVX2-NEXT:    vextractf128 $1, %ymm2, (%rcx)
+; AVX2-NEXT:    vmovdqa %xmm5, (%r8)
+; AVX2-NEXT:    vmovdqa %xmm1, (%r9)
----------------
kito-cheng wrote:

`InVT.isSimple()` become true since v10i64 added into MVT, and then trigger reduceBuildVecToShuffle for BUILD_VECTOR.

https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L23358-L23381

DAG dump (+ means new dumps after v10i64 added into MVT):

```diff
 t30: v2i64 = BUILD_VECTOR t27, t29
+Combining: t30: v2i64 = BUILD_VECTOR t27, t29
+Creating new node: t48: v4i64 = extract_subvector t15, Constant:i64<4>
+Creating new node: t49: v4i64 = extract_subvector t15, Constant:i64<0>
+Creating new node: t50: v4i64 = vector_shuffle<2,7,u,u> t49, t48
+Creating new node: t51: v2i64 = extract_subvector t50, Constant:i64<0>
+ ... into: t51: v2i64 = extract_subvector t50, Constant:i64<0>
+
+Combining: t51: v2i64 = extract_subvector t50, Constant:i64<0>
```

backtrace:
```
#0  (anonymous namespace)::DAGCombiner::reduceBuildVecToShuffle (this=0x7fffffffc4b0, N=0x555555709880)
    at /home/kitoc/llvm-workspace/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23359
#1  0x00007fffedcfe627 in (anonymous namespace)::DAGCombiner::visitBUILD_VECTOR (this=0x7fffffffc4b0, N=0x555555709880)
    at /home/kitoc/llvm-workspace/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:23766
#2  0x00007fffedc6e776 in (anonymous namespace)::DAGCombiner::visit (this=0x7fffffffc4b0, N=0x555555709880)
    at /home/kitoc/llvm-workspace/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1950
#3  0x00007fffedc6ea1d in (anonymous namespace)::DAGCombiner::combine (this=0x7fffffffc4b0, N=0x555555709880)
    at /home/kitoc/llvm-workspace/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1997
#4  0x00007fffedc6db0f in (anonymous namespace)::DAGCombiner::Run (this=0x7fffffffc4b0, AtLevel=llvm::BeforeLegalizeTypes)
    at /home/kitoc/llvm-workspace/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1779
```

https://github.com/llvm/llvm-project/pull/96481