[llvm] [AArch64][SVE] optimisation for unary SVE store intrinsics with no active lanes (PR #95793)

via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 24 06:15:35 PDT 2024


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@@ -1417,6 +1427,10 @@ instCombineSVEST1(InstCombiner &IC, IntrinsicInst &II, const DataLayout &DL) {
   Value *Pred = II.getOperand(1);
   Value *PtrOp = II.getOperand(2);
 
+  // Remove when all lanes are inactive
+  if (auto II_NA = instCombineSVENoActiveUnaryErase(IC, II, 0))
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CarolineConcatto wrote:

I would expect this to be:
auto II_NA = instCombineSVENoActiveUnaryErase(IC, II, 1)), because in line 1427 is shows the predicate as 1
 Value *Pred = II.getOperand(1);
Same for line 1793.
Am I missing something here?

https://github.com/llvm/llvm-project/pull/95793


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