[llvm] [llvm][CodeGen] Fix failure in window scheduler caused by weak dependencies (PR #95636)

[Hua Tian via llvm-commits]

https://github.com/huaatian created https://github.com/llvm/llvm-project/pull/95636

This commit addresses an issue where weak dependencies trigger an
assertion in the window scheduler under certain conditions.


>From 9f9f0689748351814ac777fcaf70bcd500234cc7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=9Cakiratian=E2=80=9D?= <akiratian at tencent.com>
Date: Sat, 15 Jun 2024 14:42:50 +0800
Subject: [PATCH] [llvm][CodeGen] Fix failure in window scheduler caused by
 weak dependencies

This commit addresses an issue where weak dependencies trigger an
assertion in the window scheduler under certain conditions.
---
 llvm/lib/CodeGen/WindowScheduler.cpp          |  4 +-
 llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir | 39 +++++++++++++++++++
 2 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir

diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 7a7e4ca979925..418309bc9dbf5 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -422,6 +422,8 @@ int WindowScheduler::calculateMaxCycle(ScheduleDAGInstrs &DAG,
     int ExpectCycle = CurCycle;
     // The predecessors of current MI determine its earliest issue cycle.
     for (auto &Pred : SU->Preds) {
+      if (Pred.isWeak())
+        continue;
       auto *PredMI = Pred.getSUnit()->getInstr();
       int PredCycle = getOriCycle(PredMI);
       ExpectCycle = std::max(ExpectCycle, PredCycle + (int)Pred.getLatency());
@@ -479,7 +481,7 @@ int WindowScheduler::calculateStallCycle(unsigned Offset, int MaxCycle) {
     auto *SU = TripleDAG->getSUnit(&MI);
     int DefCycle = getOriCycle(&MI);
     for (auto &Succ : SU->Succs) {
-      if (Succ.getSUnit() == &TripleDAG->ExitSU)
+      if (Succ.isWeak() || Succ.getSUnit() == &TripleDAG->ExitSU)
         continue;
       // If the expected cycle does not exceed MaxCycle, no check is needed.
       if (DefCycle + (int)Succ.getLatency() <= MaxCycle)
diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir b/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
new file mode 100644
index 0000000000000..72fb98cf4978a
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/swp-ws-weak-dep.mir
@@ -0,0 +1,39 @@
+# REQUIRES: asserts
+# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
+# RUN: -window-sched=force -o - 2>&1 | FileCheck %s
+
+# CHECK: SU(3): Ord  Latency=0 Weak
+# CHECK: SU(1): Ord  Latency=0 Weak
+# CHECK: Window scheduling is not needed!
+
+---
+name:            khazad_setkey_in_key
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $r0, $r1
+  
+    %0:intregs = COPY $r1
+    %1:intregs = COPY $r0
+    J2_loop0i %bb.1, 1, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+  
+  bb.1:
+    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
+  
+    %2:doubleregs = L2_loadrd_io %1, 0
+    %3:intregs = COPY %2.isub_lo
+    S2_storeri_io %0, 0, %3
+    %4:intregs = S2_asl_i_r %2.isub_hi, 2
+    %5:intregs = L2_loadri_io %4, 0
+    %6:intregs = S4_andi_asl_ri 4, %3, 1
+    %7:intregs = L2_loadri_io %6, 0
+    %8:intregs = A2_xor %7, %5
+    S2_storeri_io %1, 0, %8
+    ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+    J2_jump %bb.2, implicit-def dead $pc
+  
+  bb.2:
+    PS_jmpret $r31, implicit-def dead $pc
+
+...