[llvm] Revert " [AArch64][SME] Enable subreg liveness tracking when SME is available" (PR #95574)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 14 10:29:26 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-llvm-globalisel
Author: Florian Mayer (fmayer)
<details>
<summary>Changes</summary>
Reverts llvm/llvm-project#<!-- -->92142
For now sending this to run on CI
---
Patch is 1.08 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/95574.diff
72 Files Affected:
- (modified) llvm/lib/Target/AArch64/AArch64Subtarget.h (-1)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll (+45-45)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll (+55-55)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll (+75-75)
- (modified) llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll (+85-85)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll (+20)
- (modified) llvm/test/CodeGen/AArch64/aarch64-interleaved-access-w-undef.ll (+17-12)
- (modified) llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll (+12-12)
- (modified) llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll (+2)
- (modified) llvm/test/CodeGen/AArch64/arm64-atomic-128.ll (+42-16)
- (modified) llvm/test/CodeGen/AArch64/arm64-dup.ll (+10-5)
- (modified) llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll (+1800-72)
- (modified) llvm/test/CodeGen/AArch64/arm64-ld1.ll (+180-48)
- (modified) llvm/test/CodeGen/AArch64/arm64-neon-copy.ll (+15-3)
- (modified) llvm/test/CodeGen/AArch64/arm64-neon-copyPhysReg-tuple.ll (+19-16)
- (modified) llvm/test/CodeGen/AArch64/arm64-tbl.ll (+252-48)
- (modified) llvm/test/CodeGen/AArch64/arm64-zip.ll (+16-12)
- (modified) llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll (+2-2)
- (modified) llvm/test/CodeGen/AArch64/bf16-shuffle.ll (+18-9)
- (modified) llvm/test/CodeGen/AArch64/build-vector-two-dup.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/complex-deinterleaving-multiuses.ll (+14-14)
- (modified) llvm/test/CodeGen/AArch64/extract-vector-elt.ll (+2)
- (modified) llvm/test/CodeGen/AArch64/fp-conversion-to-tbl.ll (+17-17)
- (modified) llvm/test/CodeGen/AArch64/fptoi.ll (+140-106)
- (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+50-50)
- (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+76-76)
- (modified) llvm/test/CodeGen/AArch64/insert-subvector.ll (+10-6)
- (modified) llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll (+10-2)
- (modified) llvm/test/CodeGen/AArch64/neon-extracttruncate.ll (+4)
- (modified) llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll (+4)
- (modified) llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll (+6)
- (modified) llvm/test/CodeGen/AArch64/seqpairspill.mir (+6-6)
- (modified) llvm/test/CodeGen/AArch64/shuffle-tbl34.ll (+50-33)
- (modified) llvm/test/CodeGen/AArch64/shuffles.ll (+36-24)
- (modified) llvm/test/CodeGen/AArch64/shufflevector.ll (+77-38)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll (+24)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll (+60)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll (+4)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll (+98-2)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-fp-dots.ll (+32-20)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-insert-mova.ll (+144)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-int-dots.ll (+125-451)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll (+218-182)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll (+218-182)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll (+152-92)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll (+192-1)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll (+104-104)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll (+2)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll (+52-52)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll (+60)
- (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-vdot.ll (+43-339)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll (+119)
- (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll (+63)
- (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll (+81)
- (modified) llvm/test/CodeGen/AArch64/sve-merging-stores.ll (+5-8)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-shuffle.ll (+7-4)
- (modified) llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll (+24-16)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfclamp.ll (+6)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fclamp.ll (+18)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll (+153)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll (+24)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-selx4.ll (+64-64)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-stores.ll (+48-48)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll (+24)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uzpx4.ll (+10-10)
- (modified) llvm/test/CodeGen/AArch64/sve2p1-intrinsics-while-pp.ll (+32)
- (modified) llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll (-1)
- (modified) llvm/test/CodeGen/AArch64/tbl-loops.ll (+38-41)
- (modified) llvm/test/CodeGen/AArch64/trunc-to-tbl.ll (+6-6)
- (modified) llvm/test/CodeGen/AArch64/vldn_shuffle.ll (+42-42)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index 9912190e1bced..7ef7a89b5749f 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -149,7 +149,6 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
const Triple &getTargetTriple() const { return TargetTriple; }
bool enableMachineScheduler() const override { return true; }
bool enablePostRAScheduler() const override { return usePostRAScheduler(); }
- bool enableSubRegLiveness() const override { return true; }
bool enableMachinePipeliner() const override;
bool useDFAforSMS() const override { return false; }
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
index 444f579f23242..a1712a5ec7a27 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
@@ -2273,10 +2273,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_monotonic(ptr %ptr, i128 %val
; -O1-LABEL: atomicrmw_nand_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: casp x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: casp x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value monotonic, align 16
@@ -2298,10 +2298,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_acquire(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspa x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspa x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value acquire, align 16
@@ -2323,10 +2323,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_release(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspl x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspl x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value release, align 16
@@ -2348,10 +2348,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_acq_rel(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspal x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspal x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value acq_rel, align 16
@@ -2373,10 +2373,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_seq_cst(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspal x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspal x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value seq_cst, align 16
@@ -3406,7 +3406,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_monotonic(ptr %ptr, i128 %valu
; -O1-LABEL: atomicrmw_xor_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3427,7 +3427,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_acquire(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_xor_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3448,7 +3448,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_release(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_xor_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3469,7 +3469,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_acq_rel(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_xor_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3490,7 +3490,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_seq_cst(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_xor_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3947,7 +3947,7 @@ define dso_local i128 @atomicrmw_max_i128_aligned_monotonic(ptr %ptr, i128 %valu
; -O1-LABEL: atomicrmw_max_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lt
+; -O1: csel x9, x7, x3, lt
; -O1: csel x8, x4, x2, lt
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -3975,7 +3975,7 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acquire(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_max_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lt
+; -O1: csel x9, x7, x3, lt
; -O1: csel x8, x4, x2, lt
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4003,7 +4003,7 @@ define dso_local i128 @atomicrmw_max_i128_aligned_release(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_max_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lt
+; -O1: csel x9, x7, x3, lt
; -O1: csel x8, x4, x2, lt
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4031,7 +4031,7 @@ define dso_local i128 @atomicrmw_max_i128_aligned_acq_rel(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_max_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lt
+; -O1: csel x9, x7, x3, lt
; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4059,7 +4059,7 @@ define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_max_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lt
+; -O1: csel x9, x7, x3, lt
; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4592,7 +4592,7 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, ge
+; -O1: csel x9, x7, x3, ge
; -O1: csel x8, x4, x2, ge
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4620,7 +4620,7 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, ge
+; -O1: csel x9, x7, x3, ge
; -O1: csel x8, x4, x2, ge
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4648,7 +4648,7 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, ge
+; -O1: csel x9, x7, x3, ge
; -O1: csel x8, x4, x2, ge
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4676,7 +4676,7 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, ge
+; -O1: csel x9, x7, x3, ge
; -O1: csel x8, x4, x2, ge
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -4704,7 +4704,7 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, ge
+; -O1: csel x9, x7, x3, ge
; -O1: csel x8, x4, x2, ge
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5237,7 +5237,7 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_monotonic(ptr %ptr, i128 %val
; -O1-LABEL: atomicrmw_umax_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lo
+; -O1: csel x9, x7, x3, lo
; -O1: csel x8, x4, x2, lo
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5265,7 +5265,7 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acquire(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umax_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lo
+; -O1: csel x9, x7, x3, lo
; -O1: csel x8, x4, x2, lo
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5293,7 +5293,7 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_release(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umax_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lo
+; -O1: csel x9, x7, x3, lo
; -O1: csel x8, x4, x2, lo
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5321,7 +5321,7 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_acq_rel(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umax_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lo
+; -O1: csel x9, x7, x3, lo
; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5349,7 +5349,7 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umax_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, lo
+; -O1: csel x9, x7, x3, lo
; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5877,7 +5877,7 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, hs
+; -O1: csel x9, x7, x3, hs
; -O1: csel x8, x4, x2, hs
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5905,7 +5905,7 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, hs
+; -O1: csel x9, x7, x3, hs
; -O1: csel x8, x4, x2, hs
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5933,7 +5933,7 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, hs
+; -O1: csel x9, x7, x3, hs
; -O1: csel x8, x4, x2, hs
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5961,7 +5961,7 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, hs
+; -O1: csel x9, x7, x3, hs
; -O1: csel x8, x4, x2, hs
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
@@ -5989,7 +5989,7 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: cmp x2, x4
-; -O1: csel x9, x5, x3, hs
+; -O1: csel x9, x7, x3, hs
; -O1: csel x8, x4, x2, hs
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
index 62af028defde5..ee5fbe39b4492 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
@@ -1616,7 +1616,7 @@ define dso_local i128 @atomicrmw_and_i128_aligned_monotonic(ptr %ptr, i128 %valu
; -O1-LABEL: atomicrmw_and_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
+; -O1: and x9, x7, x3
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -1637,7 +1637,7 @@ define dso_local i128 @atomicrmw_and_i128_aligned_acquire(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_and_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
+; -O1: and x9, x7, x3
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -1658,7 +1658,7 @@ define dso_local i128 @atomicrmw_and_i128_aligned_release(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_and_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
+; -O1: and x9, x7, x3
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -1679,7 +1679,7 @@ define dso_local i128 @atomicrmw_and_i128_aligned_acq_rel(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_and_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
+; -O1: and x9, x7, x3
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -1700,7 +1700,7 @@ define dso_local i128 @atomicrmw_and_i128_aligned_seq_cst(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_and_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
+; -O1: and x9, x7, x3
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -2343,10 +2343,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_monotonic(ptr %ptr, i128 %val
; -O1-LABEL: atomicrmw_nand_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: casp x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: casp x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value monotonic, align 16
@@ -2368,10 +2368,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_acquire(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspa x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspa x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value acquire, align 16
@@ -2393,10 +2393,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_release(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspl x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspl x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value release, align 16
@@ -2418,10 +2418,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_acq_rel(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspal x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspal x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value acq_rel, align 16
@@ -2443,10 +2443,10 @@ define dso_local i128 @atomicrmw_nand_i128_aligned_seq_cst(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_nand_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: and x8, x4, x2
-; -O1: and x9, x5, x3
-; -O1: mvn x8, x8
-; -O1: mvn x9, x9
-; -O1: caspal x4, x5, x8, x9, [x0]
+; -O1: and x9, x7, x3
+; -O1: mvn x10, x8
+; -O1: mvn x11, x9
+; -O1: caspal x4, x5, x10, x11, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
%r = atomicrmw nand ptr %ptr, i128 %value seq_cst, align 16
@@ -2996,7 +2996,7 @@ define dso_local i128 @atomicrmw_or_i128_aligned_monotonic(ptr %ptr, i128 %value
; -O1-LABEL: atomicrmw_or_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: orr x8, x4, x2
-; -O1: orr x9, x5, x3
+; -O1: orr x9, x7, x3
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3017,7 +3017,7 @@ define dso_local i128 @atomicrmw_or_i128_aligned_acquire(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_or_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: orr x8, x4, x2
-; -O1: orr x9, x5, x3
+; -O1: orr x9, x7, x3
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3038,7 +3038,7 @@ define dso_local i128 @atomicrmw_or_i128_aligned_release(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_or_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: orr x8, x4, x2
-; -O1: orr x9, x5, x3
+; -O1: orr x9, x7, x3
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3059,7 +3059,7 @@ define dso_local i128 @atomicrmw_or_i128_aligned_acq_rel(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_or_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: orr x8, x4, x2
-; -O1: orr x9, x5, x3
+; -O1: orr x9, x7, x3
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3080,7 +3080,7 @@ define dso_local i128 @atomicrmw_or_i128_aligned_seq_cst(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_or_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
; -O1: orr x8, x4, x2
-; -O1: orr x9, x5, x3
+; -O1: orr x9, x7, x3
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3531,7 +3531,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_monotonic(ptr %ptr, i128 %valu
; -O1-LABEL: atomicrmw_xor_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3552,7 +3552,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_acquire(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_xor_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3573,7 +3573,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_release(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_xor_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
; -O1: eor x8, x4, x2
-; -O1: eor x9, x5, x3
+; -O1: eor x9, x7, x3
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -3594,7 +3594,7 @@ define dso_local i128 @atomicrmw_xor_i128_aligned_acq_rel(ptr %ptr, i128 %value)
; -O1-LABEL: atomicrmw_xor_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
; -O1: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/95574
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