[llvm] [MachineScheduler] Experimental option to partially disable pre-ra scheduling. (PR #90181)

[Andrew Trick via llvm-commits]

atrick wrote:

This is a typical problem with pre-ra scheduling. The pressure looks fine before scheduling. The list scheduler backs itself into a corner trying to expose ILP before it reaches the pressure limit, then can't back itself out.

It would be great if DFS subtrees can handle this case. You'll may need to dig into the design and see if it can recognize good subtrees on cactus and tweak its own heuristics, which can be sensitive. You would have to decide whether to always enable subtrees for your target (and pay any compile time cost). Or somehow identify DAG patterns where it's worth enabling subtrees.

In general, it would be awesome if the scheduler could recognize certain classes of DAGs and set the heuristics accordingly before it starts scheduling. So in this case, it should know to try to keep register pressure below the machine's limit because it will need those registers later.

Generic scheduler's strategy is to avoid perturbing the schedule unless it sees an opportunity, but that can still fail with large subtrees like this. Another approach would be a 2-pass scheduler. The first pass would expose ILP. The second pass would then know how far register pressure had been exceeded and would reschedule to avoid spills. The generic schedule doesn't do that because it's trying to be compile-time friendly and trying not to perturb the original instruction schedule.

https://github.com/llvm/llvm-project/pull/90181