[llvm] 2ed2975 - [RISCV] Add isel patterns for bf16 riscv_vfmv_v_f_vl of FP constant.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-06-14T09:33:12-07:00
New Revision: 2ed2975e8bd9e9e1a0f376bded1dad627d5eab4e

URL: https://github.com/llvm/llvm-project/commit/2ed2975e8bd9e9e1a0f376bded1dad627d5eab4e
DIFF: https://github.com/llvm/llvm-project/commit/2ed2975e8bd9e9e1a0f376bded1dad627d5eab4e.diff

LOG: [RISCV] Add isel patterns for bf16 riscv_vfmv_v_f_vl of FP constant.

We try not let bf16 splats through to isel, but constant folding
allows FP constants to get through. Thankfully we can handle those
using vmv.v.i or vmv.v.x.

Added: 
    llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 372f2c5bbf9f1..a7945f2ee6c1b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2654,7 +2654,7 @@ foreach fvti = AllFloatVectors in {
   }
 }
 
-foreach fvti = AllFloatVectors in {
+foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in {
   defvar ivti = GetIntVTypeInfo<fvti>.Vti;
   let Predicates = GetVTypePredicates<ivti>.Predicates in {
     // 13.16. Vector Floating-Point Move Instruction
@@ -2668,7 +2668,9 @@ foreach fvti = AllFloatVectors in {
               (!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX)
                $passthru, GPR:$imm, GPR:$vl, fvti.Log2SEW, TU_MU)>;
   }
+}
 
+foreach fvti = AllFloatVectors in {
   let Predicates = GetVTypePredicates<fvti>.Predicates in {
     def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
                            fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll
new file mode 100644
index 0000000000000..26eb55e5f93aa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-bf16.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+experimental-zfbfmin,+experimental-zvfbfmin,+v -target-abi ilp32d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zfbfmin,+experimental-zvfbfmin,+v -target-abi lp64d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define <vscale x 8 x bfloat> @vsplat_zero_nxv8f16() {
+; CHECK-LABEL: vsplat_zero_nxv8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    ret
+  ret <vscale x 8 x bfloat> splat (bfloat zeroinitializer)
+}
+
+define <vscale x 8 x bfloat> @vsplat_negzero_nxv8f16() {
+; CHECK-LABEL: vsplat_negzero_nxv8f16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048568
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    ret
+  ret <vscale x 8 x bfloat> splat (bfloat -0.0)
+}