[llvm] [AMDGPU] Make use of composeSubRegIndices. NFCI. (PR #95548)
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Fri Jun 14 07:00:13 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
Simplify SIInstrInfo::buildExtractSubReg by building one COPY with a
composed subreg index instead of two COPYs.
---
Full diff: https://github.com/llvm/llvm-project/pull/95548.diff
1 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+2-17)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 0edcdb337b5af..30c27b6439fc0 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5651,24 +5651,9 @@ unsigned SIInstrInfo::buildExtractSubReg(
DebugLoc DL = MI->getDebugLoc();
Register SubReg = MRI.createVirtualRegister(SubRC);
- if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
- BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
- .addReg(SuperReg.getReg(), 0, SubIdx);
- return SubReg;
- }
-
- // Just in case the super register is itself a sub-register, copy it to a new
- // value so we don't need to worry about merging its subreg index with the
- // SubIdx passed to this function. The register coalescer should be able to
- // eliminate this extra copy.
- Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
-
- BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
- .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
-
+ unsigned NewSubIdx = RI.composeSubRegIndices(SuperReg.getSubReg(), SubIdx);
BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
- .addReg(NewSuperReg, 0, SubIdx);
-
+ .addReg(SuperReg.getReg(), 0, NewSubIdx);
return SubReg;
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/95548
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