[llvm] 706e197 - [CodeGen] Remove target SubRegLiveness flags (#95437)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 14 00:52:01 PDT 2024
Author: David Green
Date: 2024-06-14T08:51:56+01:00
New Revision: 706e1975400b3f30bd406b694bb711a7c7dbe1c4
URL: https://github.com/llvm/llvm-project/commit/706e1975400b3f30bd406b694bb711a7c7dbe1c4
DIFF: https://github.com/llvm/llvm-project/commit/706e1975400b3f30bd406b694bb711a7c7dbe1c4.diff
LOG: [CodeGen] Remove target SubRegLiveness flags (#95437)
This removes the uses of target flags to disable subreg liveness,
relying on the `-enable-subreg-liveness` flag instead. The
`-enable-subreg-liveness` flag has been changed to take precedence over
the subtarget if set, and one use of `Subtarget->enableSubRegLiveness()`
has been changed to `MRI->subRegLivenessEnabled()` to make sure the
option properly applies.
Added:
Modified:
llvm/lib/CodeGen/InitUndef.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll
llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll
llvm/test/CodeGen/PowerPC/atomics-i128.ll
llvm/test/CodeGen/PowerPC/mma-outer-product.ll
llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
llvm/test/CodeGen/PowerPC/subreg-killed.mir
llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/InitUndef.cpp b/llvm/lib/CodeGen/InitUndef.cpp
index 96ac385b6abf8..51c50ff872ef2 100644
--- a/llvm/lib/CodeGen/InitUndef.cpp
+++ b/llvm/lib/CodeGen/InitUndef.cpp
@@ -238,7 +238,7 @@ bool InitUndef::processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
}
if (isEarlyClobberMI(MI)) {
- if (ST->enableSubRegLiveness())
+ if (MRI->subRegLivenessEnabled())
Changed |= handleSubReg(MF, MI, DLD);
Changed |= handleReg(&MI);
}
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index b0c1838b3ff0e..3caa96cd5e55d 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -41,8 +41,10 @@ static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,
void MachineRegisterInfo::Delegate::anchor() {}
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
- : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
- EnableSubRegLiveness) {
+ : MF(MF),
+ TracksSubRegLiveness(EnableSubRegLiveness.getNumOccurrences()
+ ? EnableSubRegLiveness
+ : MF->getSubtarget().enableSubRegLiveness()) {
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index a8c6cd99633f3..b66a41d06062f 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -68,9 +68,6 @@ static cl::opt<bool>
ForceFastISel("arm-force-fast-isel",
cl::init(false), cl::Hidden);
-static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness",
- cl::init(false), cl::Hidden);
-
/// initializeSubtargetDependencies - Initializes using a CPU and feature string
/// so that we can use initializer lists for subtarget initialization.
ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
@@ -385,8 +382,6 @@ bool ARMSubtarget::enableMachineScheduler() const {
}
bool ARMSubtarget::enableSubRegLiveness() const {
- if (EnableSubRegLiveness.getNumOccurrences())
- return EnableSubRegLiveness;
// Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
// and q subregs for qqqqpr regs.
return hasMVEIntegerOps();
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index da8ab5c4b21bb..5e713842ff674 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -55,10 +55,6 @@ static cl::opt<bool>
DisableHexagonMISched("disable-hexagon-misched", cl::Hidden,
cl::desc("Disable Hexagon MI Scheduling"));
-static cl::opt<bool> EnableSubregLiveness(
- "hexagon-subreg-liveness", cl::Hidden, cl::init(true),
- cl::desc("Enable subregister liveness tracking for Hexagon"));
-
static cl::opt<bool> OverrideLongCalls(
"hexagon-long-calls", cl::Hidden,
cl::desc("If present, forces/disables the use of long calls"));
@@ -726,9 +722,7 @@ unsigned HexagonSubtarget::getL1PrefetchDistance() const {
return 32;
}
-bool HexagonSubtarget::enableSubRegLiveness() const {
- return EnableSubregLiveness;
-}
+bool HexagonSubtarget::enableSubRegLiveness() const { return true; }
Intrinsic::ID HexagonSubtarget::getIntrinsicId(unsigned Opc) const {
struct Scalar {
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 0628fbb26245c..bd9af12b30f5e 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -37,11 +37,6 @@ using namespace llvm;
#define GET_SUBTARGETINFO_CTOR
#include "PPCGenSubtargetInfo.inc"
-static cl::opt<bool>
- UseSubRegLiveness("ppc-track-subreg-liveness",
- cl::desc("Enable subregister liveness tracking for PPC"),
- cl::init(true), cl::Hidden);
-
static cl::opt<bool>
EnableMachinePipeliner("ppc-enable-pipeliner",
cl::desc("Enable Machine Pipeliner for PPC"),
@@ -186,9 +181,7 @@ bool PPCSubtarget::useAA() const {
return true;
}
-bool PPCSubtarget::enableSubRegLiveness() const {
- return UseSubRegLiveness;
-}
+bool PPCSubtarget::enableSubRegLiveness() const { return true; }
bool PPCSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
if (isAIXABI()) {
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index d3236bb07d56d..e84ddc65e2b70 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -39,9 +39,6 @@ namespace llvm::RISCVTuneInfoTable {
#include "RISCVGenSearchableTables.inc"
} // namespace llvm::RISCVTuneInfoTable
-static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
- cl::init(true), cl::Hidden);
-
static cl::opt<unsigned> RVVVectorLMULMax(
"riscv-v-fixed-length-vector-lmul-max",
cl::desc("The maximum LMUL value to use for fixed length vectors. "
@@ -183,11 +180,7 @@ bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
}
-bool RISCVSubtarget::enableSubRegLiveness() const {
- // FIXME: Enable subregister liveness by default for RVV to better handle
- // LMUL>1 and segment load/store.
- return EnableSubRegLiveness;
-}
+bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
void RISCVSubtarget::getPostRAMutations(
std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
diff --git a/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir b/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
index bf08af763357b..2387d8b4338ef 100644
--- a/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
+++ b/llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -start-before register-coalescer -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -arm-enable-subreg-liveness -verify-machineinstrs | FileCheck %s
+# RUN: llc %s -start-before register-coalescer -mtriple=arm-apple-ios -stop-after machine-scheduler -o - -enable-subreg-liveness -verify-machineinstrs | FileCheck %s
# Check that when we merge live-ranges that imply offseting
# the definition of a subregister by some other subreg index,
diff --git a/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll b/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll
index 2857c05db764f..5d36cae76987b 100644
--- a/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll
+++ b/llvm/test/CodeGen/Hexagon/bit-gen-rseq.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -disable-hsdr -hexagon-subreg-liveness < %s | FileCheck %s
+; RUN: llc -march=hexagon -disable-hsdr -enable-subreg-liveness < %s | FileCheck %s
; Check that we don't generate any bitwise operations.
; CHECK-NOT: = or(
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
index 9468b18bf8e47..d291af97d3afd 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
@@ -1,4 +1,4 @@
-# RUN: llc -march=hexagon -hexagon-subreg-liveness -start-after machine-scheduler -stop-after stack-slot-coloring -o - %s | FileCheck %s
+# RUN: llc -march=hexagon -enable-subreg-liveness -start-after machine-scheduler -stop-after stack-slot-coloring -o - %s | FileCheck %s
--- |
target triple = "hexagon"
diff --git a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
index f4a623d74436f..8205a6c025c1b 100644
--- a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
+++ b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
@@ -1,8 +1,8 @@
# Using a trick to run register-coalescer twice, that way
# liveintervals should be preserved while running the machine verifier.
#
-# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
-# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
+# RUN: not --crash llc -o - %s -march=hexagon -enable-subreg-liveness=false -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s
+# RUN: not --crash llc -o - %s -march=hexagon -enable-subreg-liveness=true -run-pass register-coalescer -verify-machineinstrs -run-pass register-coalescer 2>&1 | FileCheck -check-prefix=CHECK-SUB %s
---
name: test_pass
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll
index 98d00b0e01b4b..8967eac223caa 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i128-ldst.ll
@@ -1,21 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
-; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-track-subreg-liveness \
+; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -enable-subreg-liveness \
; RUN: < %s | FileCheck --check-prefix=P8 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
; RUN: -ppc-asm-full-reg-names \
-; RUN: -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: -enable-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
; RUN: --check-prefix=LE-PWR8 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
; RUN: --check-prefix=LE-PWR8 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
; RUN: --check-prefix=AIX64-PWR8 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s \
; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
define dso_local i128 @lq_unordered(ptr %src) {
diff --git a/llvm/test/CodeGen/PowerPC/atomics-i128.ll b/llvm/test/CodeGen/PowerPC/atomics-i128.ll
index f5422a9b7b542..0d231769ac505 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -1,25 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr8 \
; RUN: -ppc-asm-full-reg-names \
-; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s
+; RUN: -enable-subreg-liveness < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 \
; RUN: -ppc-asm-full-reg-names \
-; RUN: -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
+; RUN: -enable-subreg-liveness < %s | FileCheck --check-prefix=PWR7 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
; RUN: --check-prefix=LE-PWR8 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-freebsd -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
; RUN: --check-prefix=LE-PWR8 %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s | FileCheck \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s | FileCheck \
; RUN: --check-prefix=AIX64-PWR8 %s
; On 32-bit PPC platform, 16-byte lock free atomic instructions are not available,
; it's expected not to generate inlined lock-free code on such platforms, even arch level
; is pwr8+ and `-ppc-quadword-atomics` is on.
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown -mcpu=pwr8 \
-; RUN: -ppc-asm-full-reg-names -ppc-track-subreg-liveness < %s \
+; RUN: -ppc-asm-full-reg-names -enable-subreg-liveness < %s \
; RUN: | FileCheck --check-prefix=PPC-PWR8 %s
diff --git a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
index 33a8260c7bf52..085b81a4c6278 100644
--- a/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-outer-product.ll
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
+; RUN: -mcpu=pwr10 -enable-subreg-liveness -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr10 -ppc-track-subreg-liveness -ppc-asm-full-reg-names \
+; RUN: -mcpu=pwr10 -enable-subreg-liveness -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
index 3823cce421440..8ba45643d5a01 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
@@ -4,7 +4,7 @@
; RUN: | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
-; RUN: -ppc-track-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
+; RUN: -enable-subreg-liveness < %s | FileCheck %s --check-prefix=TRACKLIVE
%0 = type <{ double }>
%1 = type <{ double }>
diff --git a/llvm/test/CodeGen/PowerPC/subreg-killed.mir b/llvm/test/CodeGen/PowerPC/subreg-killed.mir
index 433b9549f8a61..ae12ab995af14 100644
--- a/llvm/test/CodeGen/PowerPC/subreg-killed.mir
+++ b/llvm/test/CodeGen/PowerPC/subreg-killed.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mcpu=pwr10 -O3 -ppc-track-subreg-liveness -verify-machineinstrs \
+# RUN: llc -mcpu=pwr10 -O3 -enable-subreg-liveness -verify-machineinstrs \
# RUN: -mtriple=powerpc64le-unknown-linux-gnu -run-pass=greedy,virtregrewriter \
# RUN: -o - %s | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
index 478d2eae9dca2..a8e99ddf32d63 100644
--- a/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
+++ b/llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O2 -mtriple riscv64 -mattr=+v,+m,+zbb -riscv-enable-subreg-liveness \
+; RUN: llc -O2 -mtriple riscv64 -mattr=+v,+m,+zbb -enable-subreg-liveness \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck %s
diff --git a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
index c92ba98dcc338..9971cb7821ad1 100644
--- a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
+++ b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh \
-; RUN: -riscv-enable-subreg-liveness=false < %s | FileCheck %s
+; RUN: -enable-subreg-liveness=false < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+m,+zfh,+zvfh < %s \
-; RUN: -riscv-enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS
+; RUN: -enable-subreg-liveness=true| FileCheck %s --check-prefix=SUBREGLIVENESS
; This testcase failed to compile after
; c46aab01c002b7a04135b8b7f1f52d8c9ae23a58, which was reverted.
diff --git a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
index 9cafb323dc65c..539d319f3426d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=init-undef -o - | FileCheck %s
+# RUN: llc %s -mtriple=riscv64 -mattr=+v -enable-subreg-liveness -run-pass=init-undef -o - | FileCheck %s
...
---
diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
index 48c30596ad518..5345bec22b914 100644
--- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple riscv64 -mattr=+v -riscv-enable-subreg-liveness < %s | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+v -enable-subreg-liveness < %s | FileCheck %s
define <vscale x 2 x float> @vrgather_all_undef(ptr %p) {
; CHECK-LABEL: vrgather_all_undef:
diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
index dcf61c048ff0e..8df2c60c926c3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+v -riscv-enable-subreg-liveness -run-pass init-undef -run-pass machineverifier %s -o - | FileCheck %s
+# RUN: llc -mtriple=riscv32 -mattr=+v -enable-subreg-liveness -run-pass init-undef -run-pass machineverifier %s -o - | FileCheck %s
--- |
source_filename = "<stdin>"
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
index e95e9fabe9342..1779fc12095e8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix NOSUBREG
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -riscv-enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG
; This test checks that vrgatherei16 instructions are correctly
; register-allocated. The LMUL=1 destination register groups may not overlap
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
index 15aa62d5cff6b..0995521957b98 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=thumbv8.1m.main-none-unknown-eabi -mattr=+mve -run-pass=arm-low-overhead-loops -arm-enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple=thumbv8.1m.main-none-unknown-eabi -mattr=+mve -run-pass=arm-low-overhead-loops -enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
--- |
%struct.arm_2d_size_t = type { i16, i16 }
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir
index 898e6b15e18f1..571002cc8e8c2 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -arm-enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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