[llvm] [RFC][MC] Cache MCRegAliasIterator (PR #93510)

[Sergei Barannikov via llvm-commits]

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@@ -20,6 +20,85 @@
 
 using namespace llvm;
 
+namespace {
+/// MCRegAliasIterator enumerates all registers aliasing Reg.  This iterator
+/// does not guarantee any ordering or that entries are unique.
+class MCRegAliasIteratorImpl {
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s-barannikov wrote:

It would be just three nested loops as I can see it. Anyway, this was just a thought.

https://github.com/llvm/llvm-project/pull/93510