[llvm] cb021f5 - [RISCV] Don't use SEW=16 .vf instructions to move scalar bf16 into a vector.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 13 18:18:39 PDT 2024
Author: Craig Topper
Date: 2024-06-13T18:12:25-07:00
New Revision: cb021f5e46d259876ccf0aa24db48c10369f3d61
URL: https://github.com/llvm/llvm-project/commit/cb021f5e46d259876ccf0aa24db48c10369f3d61
DIFF: https://github.com/llvm/llvm-project/commit/cb021f5e46d259876ccf0aa24db48c10369f3d61.diff
LOG: [RISCV] Don't use SEW=16 .vf instructions to move scalar bf16 into a vector.
The instructions are only defined to operator f16 data. If the
scalar FPR register isn't properly nan-boxed, these instructions
will create a fp16 nan not a bf16 nan in the vector register.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 042b13418a200..b1b27f03252e0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1102,12 +1102,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::EXTRACT_SUBVECTOR},
VT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
- if (Subtarget.hasStdExtZfbfmin()) {
- if (Subtarget.hasVInstructionsF16())
- setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
- else
- setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
- }
+ if (Subtarget.hasStdExtZfbfmin())
+ setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
Custom);
setOperationAction(ISD::SELECT_CC, VT, Expand);
@@ -1340,12 +1336,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::EXTRACT_SUBVECTOR},
VT, Custom);
setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
- if (Subtarget.hasStdExtZfbfmin()) {
- if (Subtarget.hasVInstructionsF16())
- setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
- else
- setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
- }
+ if (Subtarget.hasStdExtZfbfmin())
+ setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
setOperationAction(
{ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
Custom);
@@ -6738,8 +6730,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
Subtarget.hasStdExtZfhminOrZhinxmin() &&
!Subtarget.hasVInstructionsF16())) ||
(Op.getValueType().getScalarType() == MVT::bf16 &&
- (Subtarget.hasVInstructionsBF16() && Subtarget.hasStdExtZfbfmin() &&
- !Subtarget.hasVInstructionsF16()))) {
+ (Subtarget.hasVInstructionsBF16() && Subtarget.hasStdExtZfbfmin()))) {
if (Op.getValueType() == MVT::nxv32f16 ||
Op.getValueType() == MVT::nxv32bf16)
return SplitVectorOp(Op, DAG);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
index d360c3f635b5c..d6f158b0c00e2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
@@ -1255,20 +1255,14 @@ define <2 x bfloat> @vpmerge_vv_v2bf16(<2 x bfloat> %va, <2 x bfloat> %vb, <2 x
}
define <2 x bfloat> @vpmerge_vf_v2bf16(bfloat %a, <2 x bfloat> %vb, <2 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpmerge_vf_v2bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
-; ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpmerge_vf_v2bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <2 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <2 x bfloat> %elt.head, <2 x bfloat> poison, <2 x i32> zeroinitializer
%v = call <2 x bfloat> @llvm.vp.merge.v2bf16(<2 x i1> %m, <2 x bfloat> %va, <2 x bfloat> %vb, i32 %evl)
@@ -1289,20 +1283,14 @@ define <4 x bfloat> @vpmerge_vv_v4bf16(<4 x bfloat> %va, <4 x bfloat> %vb, <4 x
}
define <4 x bfloat> @vpmerge_vf_v4bf16(bfloat %a, <4 x bfloat> %vb, <4 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpmerge_vf_v4bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
-; ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpmerge_vf_v4bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_v4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <4 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <4 x bfloat> %elt.head, <4 x bfloat> poison, <4 x i32> zeroinitializer
%v = call <4 x bfloat> @llvm.vp.merge.v4bf16(<4 x i1> %m, <4 x bfloat> %va, <4 x bfloat> %vb, i32 %evl)
@@ -1323,20 +1311,14 @@ define <8 x bfloat> @vpmerge_vv_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x
}
define <8 x bfloat> @vpmerge_vf_v8bf16(bfloat %a, <8 x bfloat> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpmerge_vf_v8bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli zero, a0, e16, m1, tu, ma
-; ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpmerge_vf_v8bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <8 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <8 x bfloat> %elt.head, <8 x bfloat> poison, <8 x i32> zeroinitializer
%v = call <8 x bfloat> @llvm.vp.merge.v8bf16(<8 x i1> %m, <8 x bfloat> %va, <8 x bfloat> %vb, i32 %evl)
@@ -1357,20 +1339,14 @@ define <16 x bfloat> @vpmerge_vv_v16bf16(<16 x bfloat> %va, <16 x bfloat> %vb, <
}
define <16 x bfloat> @vpmerge_vf_v16bf16(bfloat %a, <16 x bfloat> %vb, <16 x i1> %m, i32 zeroext %evl) {
-; ZVFH-LABEL: vpmerge_vf_v16bf16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli zero, a0, e16, m2, tu, ma
-; ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vpmerge_vf_v16bf16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, mu
-; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_v16bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vfmv.v.f v12, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <16 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <16 x bfloat> %elt.head, <16 x bfloat> poison, <16 x i32> zeroinitializer
%v = call <16 x bfloat> @llvm.vp.merge.v16bf16(<16 x i1> %m, <16 x bfloat> %va, <16 x bfloat> %vb, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
index e33c795169fab..d617c973dec32 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
@@ -1562,35 +1562,14 @@ define <vscale x 1 x bfloat> @vpmerge_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vs
}
define <vscale x 1 x bfloat> @vpmerge_vf_nxv1bf16(bfloat %a, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; RV32ZVFH-LABEL: vpmerge_vf_nxv1bf16:
-; RV32ZVFH: # %bb.0:
-; RV32ZVFH-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
-; RV32ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV32ZVFH-NEXT: ret
-;
-; RV64ZVFH-LABEL: vpmerge_vf_nxv1bf16:
-; RV64ZVFH: # %bb.0:
-; RV64ZVFH-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
-; RV64ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV64ZVFH-NEXT: ret
-;
-; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv1bf16:
-; RV32ZVFHMIN: # %bb.0:
-; RV32ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV32ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; RV32ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; RV32ZVFHMIN-NEXT: ret
-;
-; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv1bf16:
-; RV64ZVFHMIN: # %bb.0:
-; RV64ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV64ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
-; RV64ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; RV64ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 1 x bfloat> %elt.head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x bfloat> @llvm.vp.merge.nxv1bf16(<vscale x 1 x i1> %m, <vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 %evl)
@@ -1611,35 +1590,14 @@ define <vscale x 2 x bfloat> @vpmerge_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vs
}
define <vscale x 2 x bfloat> @vpmerge_vf_nxv2bf16(bfloat %a, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
-; RV32ZVFH-LABEL: vpmerge_vf_nxv2bf16:
-; RV32ZVFH: # %bb.0:
-; RV32ZVFH-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
-; RV32ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV32ZVFH-NEXT: ret
-;
-; RV64ZVFH-LABEL: vpmerge_vf_nxv2bf16:
-; RV64ZVFH: # %bb.0:
-; RV64ZVFH-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
-; RV64ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV64ZVFH-NEXT: ret
-;
-; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv2bf16:
-; RV32ZVFHMIN: # %bb.0:
-; RV32ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; RV32ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; RV32ZVFHMIN-NEXT: ret
-;
-; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv2bf16:
-; RV64ZVFHMIN: # %bb.0:
-; RV64ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV64ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
-; RV64ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; RV64ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_nxv2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 2 x bfloat> %elt.head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
%v = call <vscale x 2 x bfloat> @llvm.vp.merge.nxv2bf16(<vscale x 2 x i1> %m, <vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 %evl)
@@ -1660,35 +1618,14 @@ define <vscale x 4 x bfloat> @vpmerge_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vs
}
define <vscale x 4 x bfloat> @vpmerge_vf_nxv4bf16(bfloat %a, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
-; RV32ZVFH-LABEL: vpmerge_vf_nxv4bf16:
-; RV32ZVFH: # %bb.0:
-; RV32ZVFH-NEXT: vsetvli zero, a0, e16, m1, tu, ma
-; RV32ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV32ZVFH-NEXT: ret
-;
-; RV64ZVFH-LABEL: vpmerge_vf_nxv4bf16:
-; RV64ZVFH: # %bb.0:
-; RV64ZVFH-NEXT: vsetvli zero, a0, e16, m1, tu, ma
-; RV64ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV64ZVFH-NEXT: ret
-;
-; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv4bf16:
-; RV32ZVFHMIN: # %bb.0:
-; RV32ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32ZVFHMIN-NEXT: vfmv.v.f v10, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; RV32ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
-; RV32ZVFHMIN-NEXT: ret
-;
-; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv4bf16:
-; RV64ZVFHMIN: # %bb.0:
-; RV64ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV64ZVFHMIN-NEXT: vfmv.v.f v10, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, mu
-; RV64ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
-; RV64ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 4 x bfloat> %elt.head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
%v = call <vscale x 4 x bfloat> @llvm.vp.merge.nxv4bf16(<vscale x 4 x i1> %m, <vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 %evl)
@@ -1709,35 +1646,14 @@ define <vscale x 8 x bfloat> @vpmerge_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vs
}
define <vscale x 8 x bfloat> @vpmerge_vf_nxv8bf16(bfloat %a, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; RV32ZVFH-LABEL: vpmerge_vf_nxv8bf16:
-; RV32ZVFH: # %bb.0:
-; RV32ZVFH-NEXT: vsetvli zero, a0, e16, m2, tu, ma
-; RV32ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV32ZVFH-NEXT: ret
-;
-; RV64ZVFH-LABEL: vpmerge_vf_nxv8bf16:
-; RV64ZVFH: # %bb.0:
-; RV64ZVFH-NEXT: vsetvli zero, a0, e16, m2, tu, ma
-; RV64ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV64ZVFH-NEXT: ret
-;
-; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv8bf16:
-; RV32ZVFHMIN: # %bb.0:
-; RV32ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32ZVFHMIN-NEXT: vfmv.v.f v12, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, mu
-; RV32ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
-; RV32ZVFHMIN-NEXT: ret
-;
-; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv8bf16:
-; RV64ZVFHMIN: # %bb.0:
-; RV64ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV64ZVFHMIN-NEXT: vfmv.v.f v12, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, mu
-; RV64ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
-; RV64ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_nxv8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vfmv.v.f v12, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 8 x bfloat> %elt.head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x bfloat> @llvm.vp.merge.nxv8bf16(<vscale x 8 x i1> %m, <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 %evl)
@@ -1758,35 +1674,14 @@ define <vscale x 16 x bfloat> @vpmerge_vv_nxv16bf16(<vscale x 16 x bfloat> %va,
}
define <vscale x 16 x bfloat> @vpmerge_vf_nxv16bf16(bfloat %a, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
-; RV32ZVFH-LABEL: vpmerge_vf_nxv16bf16:
-; RV32ZVFH: # %bb.0:
-; RV32ZVFH-NEXT: vsetvli zero, a0, e16, m4, tu, ma
-; RV32ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV32ZVFH-NEXT: ret
-;
-; RV64ZVFH-LABEL: vpmerge_vf_nxv16bf16:
-; RV64ZVFH: # %bb.0:
-; RV64ZVFH-NEXT: vsetvli zero, a0, e16, m4, tu, ma
-; RV64ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV64ZVFH-NEXT: ret
-;
-; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv16bf16:
-; RV32ZVFHMIN: # %bb.0:
-; RV32ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfmv.v.f v16, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, tu, mu
-; RV32ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
-; RV32ZVFHMIN-NEXT: ret
-;
-; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv16bf16:
-; RV64ZVFHMIN: # %bb.0:
-; RV64ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfmv.v.f v16, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, tu, mu
-; RV64ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
-; RV64ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_nxv16bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v16, fa5
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
+; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 16 x bfloat> %elt.head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
%v = call <vscale x 16 x bfloat> @llvm.vp.merge.nxv16bf16(<vscale x 16 x i1> %m, <vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 %evl)
@@ -1807,41 +1702,17 @@ define <vscale x 32 x bfloat> @vpmerge_vv_nxv32bf16(<vscale x 32 x bfloat> %va,
}
define <vscale x 32 x bfloat> @vpmerge_vf_nxv32bf16(bfloat %a, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
-; RV32ZVFH-LABEL: vpmerge_vf_nxv32bf16:
-; RV32ZVFH: # %bb.0:
-; RV32ZVFH-NEXT: vsetvli zero, a0, e16, m8, tu, ma
-; RV32ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV32ZVFH-NEXT: ret
-;
-; RV64ZVFH-LABEL: vpmerge_vf_nxv32bf16:
-; RV64ZVFH: # %bb.0:
-; RV64ZVFH-NEXT: vsetvli zero, a0, e16, m8, tu, ma
-; RV64ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; RV64ZVFH-NEXT: ret
-;
-; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv32bf16:
-; RV32ZVFHMIN: # %bb.0:
-; RV32ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV32ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfmv.v.f v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; RV32ZVFHMIN-NEXT: vfncvtbf16.f.f.w v16, v24
-; RV32ZVFHMIN-NEXT: vmv.v.v v20, v16
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, tu, ma
-; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32ZVFHMIN-NEXT: ret
-;
-; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv32bf16:
-; RV64ZVFHMIN: # %bb.0:
-; RV64ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfmv.v.f v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; RV64ZVFHMIN-NEXT: vfncvtbf16.f.f.w v16, v24
-; RV64ZVFHMIN-NEXT: vmv.v.v v20, v16
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV64ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vpmerge_vf_nxv32bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v24, fa5
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; CHECK-NEXT: vfncvtbf16.f.f.w v16, v24
+; CHECK-NEXT: vmv.v.v v20, v16
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 32 x bfloat> %elt.head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
%v = call <vscale x 32 x bfloat> @llvm.vp.merge.nxv32bf16(<vscale x 32 x i1> %m, <vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
index ee7a94cf5e497..ec4b9721824c7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
@@ -524,20 +524,14 @@ define <vscale x 1 x bfloat> @vfmerge_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vs
}
define <vscale x 1 x bfloat> @vfmerge_fv_nxv1bf16(<vscale x 1 x bfloat> %va, bfloat %b, <vscale x 1 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_fv_nxv1bf16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv1bf16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
-; CHECK-ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_fv_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa5
+; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
+; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
%vc = select <vscale x 1 x i1> %cond, <vscale x 1 x bfloat> %splat, <vscale x 1 x bfloat> %va
@@ -555,20 +549,14 @@ define <vscale x 2 x bfloat> @vfmerge_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vs
}
define <vscale x 2 x bfloat> @vfmerge_fv_nxv2bf16(<vscale x 2 x bfloat> %va, bfloat %b, <vscale x 2 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_fv_nxv2bf16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv2bf16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-ZVFHMIN-NEXT: vfmv.v.f v9, fa5
-; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
-; CHECK-ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_fv_nxv2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v9, fa5
+; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
+; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
%vc = select <vscale x 2 x i1> %cond, <vscale x 2 x bfloat> %splat, <vscale x 2 x bfloat> %va
@@ -586,20 +574,14 @@ define <vscale x 4 x bfloat> @vfmerge_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vs
}
define <vscale x 4 x bfloat> @vfmerge_fv_nxv4bf16(<vscale x 4 x bfloat> %va, bfloat %b, <vscale x 4 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_fv_nxv4bf16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv4bf16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-ZVFHMIN-NEXT: vfmv.v.f v10, fa5
-; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, mu
-; CHECK-ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_fv_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa5
+; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
%vc = select <vscale x 4 x i1> %cond, <vscale x 4 x bfloat> %splat, <vscale x 4 x bfloat> %va
@@ -617,20 +599,14 @@ define <vscale x 8 x bfloat> @vfmerge_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vs
}
define <vscale x 8 x bfloat> @vfmerge_fv_nxv8bf16(<vscale x 8 x bfloat> %va, bfloat %b, <vscale x 8 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_fv_nxv8bf16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv8bf16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-ZVFHMIN-NEXT: vfmv.v.f v12, fa5
-; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, mu
-; CHECK-ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_fv_nxv8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; CHECK-NEXT: vfmv.v.f v12, fa5
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
+; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> %splat, <vscale x 8 x bfloat> %va
@@ -675,20 +651,14 @@ define <vscale x 16 x bfloat> @vfmerge_vv_nxv16bf16(<vscale x 16 x bfloat> %va,
}
define <vscale x 16 x bfloat> @vfmerge_fv_nxv16bf16(<vscale x 16 x bfloat> %va, bfloat %b, <vscale x 16 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_fv_nxv16bf16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv16bf16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-ZVFHMIN-NEXT: vfmv.v.f v16, fa5
-; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, mu
-; CHECK-ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_fv_nxv16bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v16, fa5
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
+; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 16 x bfloat> %head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
%vc = select <vscale x 16 x i1> %cond, <vscale x 16 x bfloat> %splat, <vscale x 16 x bfloat> %va
@@ -706,23 +676,17 @@ define <vscale x 32 x bfloat> @vfmerge_vv_nxv32bf16(<vscale x 32 x bfloat> %va,
}
define <vscale x 32 x bfloat> @vfmerge_fv_nxv32bf16(<vscale x 32 x bfloat> %va, bfloat %b, <vscale x 32 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_fv_nxv32bf16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv32bf16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-ZVFHMIN-NEXT: vfmv.v.f v16, fa5
-; CHECK-ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-ZVFHMIN-NEXT: vfncvtbf16.f.f.w v24, v16
-; CHECK-ZVFHMIN-NEXT: vmv.v.v v28, v24
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_fv_nxv32bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vfmv.v.f v16, fa5
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; CHECK-NEXT: vfncvtbf16.f.f.w v24, v16
+; CHECK-NEXT: vmv.v.v v28, v24
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 32 x bfloat> %head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
%vc = select <vscale x 32 x i1> %cond, <vscale x 32 x bfloat> %splat, <vscale x 32 x bfloat> %va
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