[llvm] [LLVM] Add `llvm.masked.compress` intrinsic (PR #92289)

[Lawrence Benson via llvm-commits]

lawben wrote:

In the [initial discussion](https://discourse.llvm.org/t/new-intrinsic-for-masked-vector-compress-without-store/78663/4), it sounded like zeroing out could be an issue for RISC-V (and the current scalar fallback implementation), while AVX512 and SVE (can) zero out the remaining lanes. Because of this, the poison/undef version seemed to have the most support. I guess it is a trade-off between the the performance of just "compressing" (where undef may have better performance) vs. the ergonomics of compressing with 0s in remaining lanes. 

In my opinion, the performance argument "wins" here, as it is supposed to be a faster alternative to `compressstore`. I believe the assumptions there are too strong. So going for strong guarantees again might defeat the purpose.

https://github.com/llvm/llvm-project/pull/92289