[llvm] ae4677c - [RISCV] Remove support for vfmv.v.f with bf16 type. (#95352)

[via llvm-commits]

Author: Craig Topper
Date: 2024-06-13T08:34:38-07:00
New Revision: ae4677c81aacbef17a5ecd3e693c4bad9f267c21

URL: https://github.com/llvm/llvm-project/commit/ae4677c81aacbef17a5ecd3e693c4bad9f267c21
DIFF: https://github.com/llvm/llvm-project/commit/ae4677c81aacbef17a5ecd3e693c4bad9f267c21.diff

LOG: [RISCV] Remove support for vfmv.v.f with bf16 type. (#95352)

This isn't used by clang and isn't in the rvv-intrinsic-doc.

The instruction requires Zvfh.

If the F register passed to the instruction isn't nan-boxed correctly,
the instruction will generate the wrong nan. So the instruction isn't a
generic move FPR16 to vector register instruction.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 70d8265e7be46..9fff89d3092b3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2653,7 +2653,7 @@ foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in {
   }
 }
 
-foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in {
+foreach fvti = AllFloatVectors in {
   let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
                                GetVTypeScalarPredicates<fvti>.Predicates) in {
     // 13.16. Vector Floating-Point Move Instruction

diff  --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
index c00433eba5481..81dc78ba9e050 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
@@ -528,123 +528,3 @@ entry:
 
   ret <vscale x 8 x double> %a
 }
-
-declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16(
-  <vscale x 1 x bfloat>,
-  bfloat,
-  iXLen);
-
-define <vscale x 1 x bfloat> @intrinsic_vfmv.v.f_f_nxv1bf16(bfloat %0, iXLen %1) nounwind {
-; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1bf16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    ret
-entry:
-  %a = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16(
-    <vscale x 1 x bfloat> undef,
-    bfloat %0,
-    iXLen %1)
-
-  ret <vscale x 1 x bfloat> %a
-}
-
-declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16(
-  <vscale x 2 x bfloat>,
-  bfloat,
-  iXLen);
-
-define <vscale x 2 x bfloat> @intrinsic_vfmv.v.f_f_nxv2bf16(bfloat %0, iXLen %1) nounwind {
-; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2bf16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    ret
-entry:
-  %a = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16(
-    <vscale x 2 x bfloat> undef,
-    bfloat %0,
-    iXLen %1)
-
-  ret <vscale x 2 x bfloat> %a
-}
-
-declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16(
-  <vscale x 4 x bfloat>,
-  bfloat,
-  iXLen);
-
-define <vscale x 4 x bfloat> @intrinsic_vfmv.v.f_f_nxv4bf16(bfloat %0, iXLen %1) nounwind {
-; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4bf16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    ret
-entry:
-  %a = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16(
-    <vscale x 4 x bfloat> undef,
-    bfloat %0,
-    iXLen %1)
-
-  ret <vscale x 4 x bfloat> %a
-}
-
-declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16(
-  <vscale x 8 x bfloat>,
-  bfloat,
-  iXLen);
-
-define <vscale x 8 x bfloat> @intrinsic_vfmv.v.f_f_nxv8bf16(bfloat %0, iXLen %1) nounwind {
-; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8bf16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    ret
-entry:
-  %a = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16(
-    <vscale x 8 x bfloat> undef,
-    bfloat %0,
-    iXLen %1)
-
-  ret <vscale x 8 x bfloat> %a
-}
-
-declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16(
-  <vscale x 16 x bfloat>,
-  bfloat,
-  iXLen);
-
-define <vscale x 16 x bfloat> @intrinsic_vfmv.v.f_f_nxv16bf16(bfloat %0, iXLen %1) nounwind {
-; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16bf16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    ret
-entry:
-  %a = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16(
-    <vscale x 16 x bfloat> undef,
-    bfloat %0,
-    iXLen %1)
-
-  ret <vscale x 16 x bfloat> %a
-}
-
-declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16(
-  <vscale x 32 x bfloat>,
-  bfloat,
-  iXLen);
-
-define <vscale x 32 x bfloat> @intrinsic_vfmv.v.f_f_nxv32bf16(bfloat %0, iXLen %1) nounwind {
-; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32bf16:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT:    vfmv.v.f v8, fa0
-; CHECK-NEXT:    ret
-entry:
-  %a = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16(
-    <vscale x 32 x bfloat> undef,
-    bfloat %0,
-    iXLen %1)
-
-  ret <vscale x 32 x bfloat> %a
-}