[llvm] [AArch64][GISel] Translate legal SVE formal arguments and select COPY for SVE (PR #95236)

[via llvm-commits]

================
@@ -597,8 +597,14 @@ getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
 /// Given a register bank, and size in bits, return the smallest register class
 /// that can represent that combination.
 static const TargetRegisterClass *
-getMinClassForRegBank(const RegisterBank &RB, unsigned SizeInBits,
+getMinClassForRegBank(const RegisterBank &RB, TypeSize SizeInBits,
----------------
Him188 wrote:

I think it's fine, as it's obtained from `TypeSize RegisterBankInfo::getSizeInBits()`. 

There are both `TypeSize LLT::getSizeInBytes()` and `TypeSize LLT::getSizeInBits()` so `TypeSize` itself does not have a unit.


https://github.com/llvm/llvm-project/pull/95236