[llvm] 33a24b7 - [X86] Add test coverage for #95284

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-06-13T11:24:59+01:00
New Revision: 33a24b7654b7bab229ac8140148cb9a1b1d00d1d

URL: https://github.com/llvm/llvm-project/commit/33a24b7654b7bab229ac8140148cb9a1b1d00d1d
DIFF: https://github.com/llvm/llvm-project/commit/33a24b7654b7bab229ac8140148cb9a1b1d00d1d.diff

LOG: [X86] Add test coverage for #95284

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/avg.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/avg.ll b/llvm/test/CodeGen/X86/avg.ll
index 6909430a1dde9..27938c2ffda81 100644
--- a/llvm/test/CodeGen/X86/avg.ll
+++ b/llvm/test/CodeGen/X86/avg.ll
@@ -2197,3 +2197,21 @@ define <8 x i16> @PR52131_not_zext_with_constant(<8 x i32> %a) {
   %i3 = trunc <8 x i32> %i2 to <8 x i16>
   ret <8 x i16> %i3
 }
+
+define i64 @PR95284(i32 %a0) {
+; CHECK-LABEL: PR95284:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %ecx
+; CHECK-NEXT:    decq %rcx
+; CHECK-NEXT:    shrq %rcx
+; CHECK-NEXT:    incq %rcx
+; CHECK-NEXT:    movabsq $9223372036854775806, %rax # imm = 0x7FFFFFFFFFFFFFFE
+; CHECK-NEXT:    andq %rcx, %rax
+; CHECK-NEXT:    retq
+  %ext = zext nneg i32 %a0 to i64
+  %dec = add i64 %ext, -1
+  %srl = lshr i64 %dec, 1
+  %inc = add nuw nsw i64 %srl, 1
+  %res = and i64 %inc, 9223372036854775806
+  ret i64 %res
+}