[llvm] 9890f94 - [AMDGPU][GFX12] Support disassembling MUBUF instructions with arbitrary FORMAT values. (#95243)
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Thu Jun 13 00:16:10 PDT 2024
Author: Ivan Kosarev
Date: 2024-06-13T08:16:06+01:00
New Revision: 9890f94343053029000e3ca6ca2b9889755f415a
URL: https://github.com/llvm/llvm-project/commit/9890f94343053029000e3ca6ca2b9889755f415a
DIFF: https://github.com/llvm/llvm-project/commit/9890f94343053029000e3ca6ca2b9889755f415a.diff
LOG: [AMDGPU][GFX12] Support disassembling MUBUF instructions with arbitrary FORMAT values. (#95243)
Some tools generate such instructions with the FORMAT field set to 0,
which corresponds to buf_fmt_invalid, but that should not prevent them
from being recognised on decoding.
Added:
Modified:
llvm/lib/Target/AMDGPU/BUFInstructions.td
llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 41d4ecaa430f7..01f911c2de5a8 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2454,9 +2454,15 @@ class VBUFFER_Real_gfx12<bits<8> op, BUF_Pseudo ps, string real_name> :
multiclass VBUFFER_MUBUF_Real_gfx12<bits<8> op, string real_name> {
defvar ps = !cast<MUBUF_Pseudo>(NAME);
def _gfx12 : VBUFFER_Real_gfx12<op, ps, real_name> {
- // Set the last bit of format to 1 to avoid round-trip issues, as some tools
+ // Set the format field to be 1 to avoid round-trip issues, as some tools
// print BUF_FMT_INVALID for format 0.
- let Inst{55} = 0b1;
+ let Inst{61-55} = 0b0000001;
+ }
+ // Have a version of the instruction to disassemble to for any other
+ // format field values.
+ def _gfx12_format : VBUFFER_Real<op, ps, real_name> {
+ let AsmVariantName = "NonParsable";
+ let DecoderNamespace = "GFX12";
}
}
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
index cb3b125041b9f..f2363e774cb9e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
@@ -1131,6 +1131,10 @@
# GFX12: buffer_store_b128 v[1:4], off, s[12:15], s4 offset:8388607 th:TH_STORE_BYPASS scope:SCOPE_SYS ; encoding: [0x04,0x40,0x07,0xc4,0x01,0x18,0xbc,0x00,0x00,0xff,0xff,0x7f]
0x04,0x40,0x07,0xc4,0x01,0x18,0xbc,0x00,0x00,0xff,0xff,0x7f
+# GFX12: buffer_store_b128 v[5:8], v0, s[20:23], s2 idxen th:TH_STORE_NT_WB scope:SCOPE_DEV ; encoding: [0x02,0x40,0x07,0xc4,0x05,0x28,0x78,0x80,0x00,0x00,0x00,0x00]
+# Check that we can still disassemble the instruction when the FORMAT field is not 1.
+0x02,0x40,0x07,0xc4,0x05,0x28,0x78,0x80,0x00,0x00,0x00,0x00
+
# GFX12: buffer_store_d16_format_x v1, off, s[12:15], s4 offset:8388607 ; encoding: [0x04,0x00,0x03,0xc4,0x01,0x18,0x80,0x00,0x00,0xff,0xff,0x7f]
0x04,0x00,0x03,0xc4,0x01,0x18,0x80,0x00,0x00,0xff,0xff,0x7f
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