[llvm] [RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin (PR #91936)

[Craig Topper via llvm-commits]

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@@ -1101,6 +1101,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                             ISD::EXTRACT_SUBVECTOR},
                            VT, Custom);
         setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
+        if (Subtarget.hasStdExtZfbfmin()) {
+          if (Subtarget.hasVInstructionsF16())
+            setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
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topperc wrote:

We can't use vfmv.v.f to splat a bf16 value. If the scalar F register isn't properly nan-boxed, the vector would need to be filled with a bf16 nan. The vfmv.v.f instruction would create an fp16 nan.

https://github.com/llvm/llvm-project/pull/91936