[llvm] 987b59a - [X86] SimplifyDemandedVectorEltsForTargetNode - use EVT for F16C nodes

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-06-12T19:55:39+01:00
New Revision: 987b59abd0f7353cabf2f620a61ec903a885522a

URL: https://github.com/llvm/llvm-project/commit/987b59abd0f7353cabf2f620a61ec903a885522a
DIFF: https://github.com/llvm/llvm-project/commit/987b59abd0f7353cabf2f620a61ec903a885522a.diff

LOG: [X86] SimplifyDemandedVectorEltsForTargetNode - use EVT for F16C nodes

As we allow these nodes to be created pre-legalization, we can't rely on them having a simple VT

Fixes #95278

Added: 
    llvm/test/CodeGen/X86/pr95278.ll

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 06839b662c127..88c7a4159856a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -41934,7 +41934,7 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
   case X86ISD::CVTPH2PS:
   case X86ISD::CVTPS2PH: {
     SDValue Src = Op.getOperand(0);
-    MVT SrcVT = Src.getSimpleValueType();
+    EVT SrcVT = Src.getValueType();
     APInt SrcUndef, SrcZero;
     APInt SrcElts = DemandedElts.zextOrTrunc(SrcVT.getVectorNumElements());
     if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,

diff  --git a/llvm/test/CodeGen/X86/pr95278.ll b/llvm/test/CodeGen/X86/pr95278.ll
new file mode 100644
index 0000000000000..32783696f4692
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr95278.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake-avx512 | FileCheck %s
+
+define void @PR95278(ptr %p0, ptr %p1) {
+; CHECK-LABEL: PR95278:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vcvtph2ps 2016(%rdi), %zmm0
+; CHECK-NEXT:    vextractf32x4 $3, %zmm0, %xmm0
+; CHECK-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; CHECK-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; CHECK-NEXT:    vmovd %xmm0, %eax
+; CHECK-NEXT:    movw %ax, (%rsi)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+  %load = load <1024 x half>, ptr %p0, align 2
+  %ext = fpext <1024 x half> %load to <1024 x float>
+  %shuffle = shufflevector <1024 x float> %ext, <1024 x float> poison, <1 x i32> <i32 1022>
+  %elt = extractelement <1 x float> %shuffle, i64 0
+  %trunc = fptrunc float %elt to half
+  store half %trunc, ptr %p1, align 2
+  ret void
+}