[llvm] ca33796 - [DAG] combineShiftToAVG - only create new types before LegalTypes

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-06-12T18:49:49+01:00
New Revision: ca33796d54ce6d2c711032b269caf32851c5915a

URL: https://github.com/llvm/llvm-project/commit/ca33796d54ce6d2c711032b269caf32851c5915a
DIFF: https://github.com/llvm/llvm-project/commit/ca33796d54ce6d2c711032b269caf32851c5915a.diff

LOG: [DAG] combineShiftToAVG - only create new types before LegalTypes

Fixes #95271

Added: 
    llvm/test/CodeGen/RISCV/pr95271.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index dc0e0857832ef..457b3bda5ab5d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1064,7 +1064,7 @@ static SDValue combineShiftToAVG(SDValue Op,
     return SDValue();
   if (VT.isVector())
     NVT = EVT::getVectorVT(*DAG.getContext(), NVT, VT.getVectorElementCount());
-  if (TLO.LegalOperations() && !TLI.isOperationLegal(AVGOpc, NVT)) {
+  if (TLO.LegalTypes() && !TLI.isOperationLegal(AVGOpc, NVT)) {
     // If we could not transform, and (both) adds are nuw/nsw, we can use the
     // larger type size to do the transform.
     if (TLO.LegalOperations() && !TLI.isOperationLegal(AVGOpc, VT))

diff  --git a/llvm/test/CodeGen/RISCV/pr95271.ll b/llvm/test/CodeGen/RISCV/pr95271.ll
new file mode 100644
index 0000000000000..950e6fb5f37ec
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr95271.ll
@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s
+
+define i32 @PR95271(ptr %p) {
+; RV32I-LABEL: PR95271:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lw a0, 0(a0)
+; RV32I-NEXT:    addi a0, a0, 1
+; RV32I-NEXT:    srli a1, a0, 1
+; RV32I-NEXT:    lui a2, 349525
+; RV32I-NEXT:    addi a2, a2, 1365
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    sub a0, a0, a1
+; RV32I-NEXT:    lui a1, 209715
+; RV32I-NEXT:    addi a1, a1, 819
+; RV32I-NEXT:    and a2, a0, a1
+; RV32I-NEXT:    srli a0, a0, 2
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    add a0, a2, a0
+; RV32I-NEXT:    srli a1, a0, 4
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    lui a1, 61681
+; RV32I-NEXT:    addi a1, a1, -241
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    slli a1, a0, 8
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    slli a1, a0, 16
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    srli a0, a0, 24
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: PR95271:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lw a0, 0(a0)
+; RV64I-NEXT:    addiw a1, a0, 1
+; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    srli a0, a0, 1
+; RV64I-NEXT:    lui a2, 349525
+; RV64I-NEXT:    addiw a2, a2, 1365
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    sub a1, a1, a0
+; RV64I-NEXT:    lui a0, 209715
+; RV64I-NEXT:    addiw a0, a0, 819
+; RV64I-NEXT:    and a2, a1, a0
+; RV64I-NEXT:    srli a1, a1, 2
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    add a0, a2, a0
+; RV64I-NEXT:    srli a1, a0, 4
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    lui a1, 61681
+; RV64I-NEXT:    addi a1, a1, -241
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    slli a1, a0, 8
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    slli a1, a0, 16
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    srliw a0, a0, 24
+; RV64I-NEXT:    ret
+  %load = load i32, ptr %p, align 4
+  %inc = add i32 %load, 1
+  %pop = tail call i32 @llvm.ctpop.i32(i32 %inc)
+  ret i32 %pop
+}