[llvm] [DAG] Add legalization handling for AVGCEIL/AVGFLOOR nodes (PR #92096)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

> Hi @RKSimon, I think this patch causes some regressions on riscv: [dtcxzyw/llvm-codegen-benchmark at 97ad8e7](https://github.com/dtcxzyw/llvm-codegen-benchmark/commit/97ad8e7b80da7aba30042b112095724802189681)
> 
> Reproducer:
> 
> ```
> ; llc -mtriple=riscv64 test.ll -o -
> define signext i64 @func000000000000002b(i32 signext %0) #0 {
> entry:
>   %1 = zext nneg i32 %0 to i64
>   %2 = add nsw i64 %1, -1
>   %3 = lshr i64 %2, 1
>   %4 = add nuw nsw i64 %3, 1
>   %5 = and i64 %4, 9223372036854775806
>   ret i64 %5
> }
> ```
> 
> Before ([74f200b](https://github.com/llvm/llvm-project/commit/74f200baedfed496880ca86ce9409788b0d0eaca)):
> 
> ```
> func000000000000002b:
>         addi    a0, a0, -1
>         srli    a0, a0, 1
>         addi    a0, a0, 1
>         andi    a0, a0, -2
>         ret
> ```
> 
> After ([47afa10](https://github.com/llvm/llvm-project/commit/47afa10bbaa89351afa9bcc53dd959e6181ebf3d)):
> 
> ```
> func000000000000002b:
>         addi    a0, a0, -1
>         srli    a0, a0, 1
>         addi    a0, a0, 1
>         li      a1, -3
>         srli    a1, a1, 1
>         and     a0, a0, a1
>         ret
> ```

```
SelectionDAG has 17 nodes:
  t0: ch,glue = EntryToken
                  t2: i64,ch = CopyFromReg t0, Register:i64 %0
                t4: i64 = AssertSext t2, ValueType:ch:i32
              t5: i32 = truncate t4
            t6: i64 = sign_extend t5
          t8: i64 = add nsw t6, Constant:i64<-1>
        t10: i64 = srl t8, Constant:i64<1>
      t11: i64 = add nuw nsw t10, Constant:i64<1>
    t13: i64 = and t11, Constant:i64<9223372036854775806>
  t15: ch,glue = CopyToReg t0, Register:i64 $x10, t13
  t16: ch = RISCVISD::RET_GLUE t15, Register:i64 $x10, t15:1



Combining: t16: ch = RISCVISD::RET_GLUE t15, Register:i64 $x10, t15:1

Combining: t15: ch,glue = CopyToReg t0, Register:i64 $x10, t13

Combining: t14: i64 = Register $x10

Combining: t13: i64 = and t11, Constant:i64<9223372036854775806>
Creating constant: t17: i32 = Constant<-1>
Creating new node: t18: i32 = avgfloors t5, Constant:i32<-1>
Creating new node: t19: i64 = sign_extend t18
```

https://github.com/llvm/llvm-project/pull/92096