[llvm] [AMDGPU][GFX12] Support disassembling MUBUF instructions with arbitrary FORMAT values. (PR #95243)

[Ivan Kosarev via llvm-commits]

https://github.com/kosarev updated https://github.com/llvm/llvm-project/pull/95243

>From fecfaaabdf71618904a31c6686c467a33cadaab1 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Wed, 12 Jun 2024 13:56:47 +0100
Subject: [PATCH 1/3] [AMDGPU][GFX12] Support disassembling MUBUF instructions
 with arbitrary FORMAT values.

Some tools generate such instructions with the FORMAT field set
to 0, which corresponds to buf_fmt_invalid, but that should not
prevent them from being recognised on decoding.
---
 llvm/lib/Target/AMDGPU/BUFInstructions.td                 | 8 +++++++-
 .../MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt   | 4 ++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index b05834e5803a2..cccd1e8906079 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2447,7 +2447,13 @@ multiclass VBUFFER_MUBUF_Real_gfx12<bits<8> op, string real_name> {
   def _gfx12 : VBUFFER_Real_gfx12<op, ps, real_name> {
     // Set the last bit of format to 1 to avoid round-trip issues, as some tools
     // print BUF_FMT_INVALID for format 0.
-    let Inst{55} = 0b1;
+    let Inst{61-55} = 1;
+  }
+  // Have a version of the instruction to disassemble to for any other
+  // FORMAT field values.
+  def _gfx12_format : VBUFFER_Real<op, ps, real_name> {
+    let AsmVariantName = "NonParsable";
+    let DecoderNamespace = "GFX12";
   }
 }
 
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
index cb3b125041b9f..f2363e774cb9e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
@@ -1131,6 +1131,10 @@
 # GFX12: buffer_store_b128 v[1:4], off, s[12:15], s4 offset:8388607 th:TH_STORE_BYPASS scope:SCOPE_SYS ; encoding:  [0x04,0x40,0x07,0xc4,0x01,0x18,0xbc,0x00,0x00,0xff,0xff,0x7f]
 0x04,0x40,0x07,0xc4,0x01,0x18,0xbc,0x00,0x00,0xff,0xff,0x7f
 
+# GFX12: buffer_store_b128 v[5:8], v0, s[20:23], s2 idxen th:TH_STORE_NT_WB scope:SCOPE_DEV ; encoding:  [0x02,0x40,0x07,0xc4,0x05,0x28,0x78,0x80,0x00,0x00,0x00,0x00]
+# Check that we can still disassemble the instruction when the FORMAT field is not 1.
+0x02,0x40,0x07,0xc4,0x05,0x28,0x78,0x80,0x00,0x00,0x00,0x00
+
 # GFX12: buffer_store_d16_format_x v1, off, s[12:15], s4 offset:8388607 ; encoding:  [0x04,0x00,0x03,0xc4,0x01,0x18,0x80,0x00,0x00,0xff,0xff,0x7f]
 0x04,0x00,0x03,0xc4,0x01,0x18,0x80,0x00,0x00,0xff,0xff,0x7f
 

>From caf984fd4e8fbf2f7fec3f7cc06bca2b9ad7c940 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Wed, 12 Jun 2024 14:32:08 +0100
Subject: [PATCH 2/3] Update comments.

---
 llvm/lib/Target/AMDGPU/BUFInstructions.td | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index cccd1e8906079..eaa6f220e1de0 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2445,12 +2445,12 @@ class VBUFFER_Real_gfx12<bits<8> op, BUF_Pseudo ps, string real_name> :
 multiclass VBUFFER_MUBUF_Real_gfx12<bits<8> op, string real_name> {
   defvar ps = !cast<MUBUF_Pseudo>(NAME);
   def _gfx12 : VBUFFER_Real_gfx12<op, ps, real_name> {
-    // Set the last bit of format to 1 to avoid round-trip issues, as some tools
+    // Set the format field to be 1 to avoid round-trip issues, as some tools
     // print BUF_FMT_INVALID for format 0.
     let Inst{61-55} = 1;
   }
   // Have a version of the instruction to disassemble to for any other
-  // FORMAT field values.
+  // format field values.
   def _gfx12_format : VBUFFER_Real<op, ps, real_name> {
     let AsmVariantName = "NonParsable";
     let DecoderNamespace = "GFX12";

>From 4a44e540c1d700f887eeb76b2f1b6f73551fe98e Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Wed, 12 Jun 2024 14:36:42 +0100
Subject: [PATCH 3/3] Change the spelling of the format field value for the
 _gfx12 variant.

---
 llvm/lib/Target/AMDGPU/BUFInstructions.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index eaa6f220e1de0..94aa75b3d532e 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -2447,7 +2447,7 @@ multiclass VBUFFER_MUBUF_Real_gfx12<bits<8> op, string real_name> {
   def _gfx12 : VBUFFER_Real_gfx12<op, ps, real_name> {
     // Set the format field to be 1 to avoid round-trip issues, as some tools
     // print BUF_FMT_INVALID for format 0.
-    let Inst{61-55} = 1;
+    let Inst{61-55} = 0b0000001;
   }
   // Have a version of the instruction to disassemble to for any other
   // format field values.