[llvm] DAG: Replace bitwidth with type in suffix in atomic tablegen ops (PR #94845)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> Though I'll note that it would be nice to have unsuffixed ops, like we do for most ops, so you can just let TableGen's inference figure it out when you're not dealing with values less than the register size.

I'm not sure why atomics ended up doing this, but I'd guess it's related to the mistake of having ATOMIC_LOAD be a separate opcode from LOAD. ATOMIC_LOAD/STORE never really consistently handled the extload/truncstore cases, which was then copied to the atomicrmw

https://github.com/llvm/llvm-project/pull/94845