[llvm] [MachinePipeliner] Improve loop carried dependence analysis (PR #94185)

[Yuta Mukai via llvm-commits]

ytmukai wrote:

Here is an example of incorrect scheduling in the current implementation.
https://godbolt.org/z/nv9aWcfsW

The increment per iteration of the address is -4, but it is erroneously recognized as 4.

```
    %0:intregs = PHI %11, %bb.0, %6, %bb.1
    %7:intregs = A2_addi %0, -8
    %6:intregs = A2_addi %7, 4
```

Therefore, loop carried dependence from store to load is ignored.

```
    %4:intregs = L2_loadri_io %0, 0 :: (load (s32))
    S2_storeri_io %0, -4, %42 :: (store (s32))
```

This results in an incorrect schedule in which the next iteration's load precedes the store.

```
	insert at cycle 0   %4:intregs = L2_loadri_io %2:intregs, 0 :: (load (s32))
	insert at cycle 3   %7:intregs = A2_addi %6:intregs, 1
Schedule Found? 1 (II=2)
```

If `TargetInstrInfo::getIncrementValue()` is not implemented, it is conservatively assumed to exist a dependency, so this problem does not occur except for Hexagon which implements it. I would like to solve this and then implement it for AArch64.

https://github.com/llvm/llvm-project/pull/94185