[llvm] 46c05df - Apply the `AdjustICmpImmAndPred` optimization when it results in a one-instruction immediate materialization over a two-instruction materialization. (#83218)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 11 17:24:00 PDT 2024
Author: Owen Anderson
Date: 2024-06-11T14:53:51-09:30
New Revision: 46c05dfb6c98870f8416eeb9bf787d54ac806b12
URL: https://github.com/llvm/llvm-project/commit/46c05dfb6c98870f8416eeb9bf787d54ac806b12
DIFF: https://github.com/llvm/llvm-project/commit/46c05dfb6c98870f8416eeb9bf787d54ac806b12.diff
LOG: Apply the `AdjustICmpImmAndPred` optimization when it results in a one-instruction immediate materialization over a two-instruction materialization. (#83218)
https://github.com/llvm/llvm-project/issues/76460
Added:
llvm/test/CodeGen/AArch64/icmp-cst.ll
Modified:
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 77b8cbe5793c3..4a1977ba1a00f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -19,6 +19,7 @@
///
//===----------------------------------------------------------------------===//
+#include "AArch64ExpandImm.h"
#include "AArch64GlobalISelUtils.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64Subtarget.h"
@@ -563,7 +564,8 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
auto ValAndVReg = getIConstantVRegValWithLookThrough(RHS, MRI);
if (!ValAndVReg)
return std::nullopt;
- uint64_t C = ValAndVReg->Value.getZExtValue();
+ uint64_t OriginalC = ValAndVReg->Value.getZExtValue();
+ uint64_t C = OriginalC;
if (isLegalArithImmed(C))
return std::nullopt;
@@ -633,9 +635,20 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
// predicate if it is.
if (Size == 32)
C = static_cast<uint32_t>(C);
- if (!isLegalArithImmed(C))
- return std::nullopt;
- return {{C, P}};
+ if (isLegalArithImmed(C))
+ return {{C, P}};
+
+ auto IsMaterializableInSingleInstruction = [=](uint64_t Imm) {
+ SmallVector<AArch64_IMM::ImmInsnModel> Insn;
+ AArch64_IMM::expandMOVImm(Imm, 32, Insn);
+ return Insn.size() == 1;
+ };
+
+ if (!IsMaterializableInSingleInstruction(OriginalC) &&
+ IsMaterializableInSingleInstruction(C))
+ return {{C, P}};
+
+ return std::nullopt;
}
/// Determine whether or not it is possible to update the RHS and predicate of
diff --git a/llvm/test/CodeGen/AArch64/icmp-cst.ll b/llvm/test/CodeGen/AArch64/icmp-cst.ll
new file mode 100644
index 0000000000000..b6f452bb42cec
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/icmp-cst.ll
@@ -0,0 +1,687 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=0 < %s | FileCheck %s --check-prefix=CHECK-SD
+; RUN: llc -mtriple=aarch64-linux-gnu -global-isel=1 < %s | FileCheck %s --check-prefix=CHECK-GI
+
+define i1 @ule_11111111(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_11111111:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #4370 // =0x1112
+; CHECK-SD-NEXT: movk w8, #4369, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_11111111:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #286331153 // =0x11111111
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, 286331154
+ ret i1 %out
+}
+
+define i1 @ule_22222222(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_22222222:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #8739 // =0x2223
+; CHECK-SD-NEXT: movk w8, #8738, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_22222222:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #572662306 // =0x22222222
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, 572662307
+ ret i1 %out
+}
+
+define i1 @ule_33333333(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_33333333:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #13108 // =0x3334
+; CHECK-SD-NEXT: movk w8, #13107, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_33333333:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #858993459 // =0x33333333
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, 858993460
+ ret i1 %out
+}
+
+define i1 @ule_44444444(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_44444444:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #17477 // =0x4445
+; CHECK-SD-NEXT: movk w8, #17476, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_44444444:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1145324612 // =0x44444444
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, 1145324613
+ ret i1 %out
+}
+
+define i1 @ule_55555555(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_55555555:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #21846 // =0x5556
+; CHECK-SD-NEXT: movk w8, #21845, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_55555555:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1431655765 // =0x55555555
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, 1431655766
+ ret i1 %out
+}
+
+define i1 @ule_66666666(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_66666666:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #26215 // =0x6667
+; CHECK-SD-NEXT: movk w8, #26214, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_66666666:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1717986918 // =0x66666666
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, 1717986919
+ ret i1 %out
+}
+
+define i1 @ule_77777777(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_77777777:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #30584 // =0x7778
+; CHECK-SD-NEXT: movk w8, #30583, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_77777777:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #2004318071 // =0x77777777
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, 2004318072
+ ret i1 %out
+}
+
+define i1 @ule_88888888(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_88888888:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #34953 // =0x8889
+; CHECK-SD-NEXT: movk w8, #34952, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_88888888:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-2004318072 // =0x88888888
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, -2004318071
+ ret i1 %out
+}
+
+define i1 @ule_99999999(i32 noundef %in) {
+; CHECK-SD-LABEL: ule_99999999:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #39322 // =0x999a
+; CHECK-SD-NEXT: movk w8, #39321, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ule_99999999:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-1717986919 // =0x99999999
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, -1717986918
+ ret i1 %out
+}
+
+define i1 @uge_11111111(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_11111111:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #4368 // =0x1110
+; CHECK-SD-NEXT: movk w8, #4369, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_11111111:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #286331153 // =0x11111111
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, 286331152
+ ret i1 %out
+}
+
+define i1 @uge_22222222(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_22222222:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #8737 // =0x2221
+; CHECK-SD-NEXT: movk w8, #8738, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_22222222:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #572662306 // =0x22222222
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, 572662305
+ ret i1 %out
+}
+
+define i1 @uge_33333333(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_33333333:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #13106 // =0x3332
+; CHECK-SD-NEXT: movk w8, #13107, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_33333333:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #858993459 // =0x33333333
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, 858993458
+ ret i1 %out
+}
+
+define i1 @uge_44444444(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_44444444:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #17475 // =0x4443
+; CHECK-SD-NEXT: movk w8, #17476, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_44444444:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1145324612 // =0x44444444
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, 1145324611
+ ret i1 %out
+}
+
+define i1 @uge_55555555(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_55555555:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #21844 // =0x5554
+; CHECK-SD-NEXT: movk w8, #21845, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_55555555:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1431655765 // =0x55555555
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, 1431655764
+ ret i1 %out
+}
+
+define i1 @uge_66666666(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_66666666:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #26213 // =0x6665
+; CHECK-SD-NEXT: movk w8, #26214, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_66666666:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1717986918 // =0x66666666
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, 1717986917
+ ret i1 %out
+}
+
+define i1 @uge_77777777(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_77777777:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #30582 // =0x7776
+; CHECK-SD-NEXT: movk w8, #30583, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_77777777:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #2004318071 // =0x77777777
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, 2004318070
+ ret i1 %out
+}
+
+define i1 @uge_88888888(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_88888888:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #34951 // =0x8887
+; CHECK-SD-NEXT: movk w8, #34952, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_88888888:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-2004318072 // =0x88888888
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, -2004318073
+ ret i1 %out
+}
+
+define i1 @uge_99999999(i32 noundef %in) {
+; CHECK-SD-LABEL: uge_99999999:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #39320 // =0x9998
+; CHECK-SD-NEXT: movk w8, #39321, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uge_99999999:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-1717986919 // =0x99999999
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, -1717986920
+ ret i1 %out
+}
+
+define i1 @sle_11111111(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_11111111:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #4370 // =0x1112
+; CHECK-SD-NEXT: movk w8, #4369, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_11111111:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #286331153 // =0x11111111
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
+ %out = icmp slt i32 %in, 286331154
+ ret i1 %out
+}
+
+define i1 @sle_22222222(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_22222222:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #8739 // =0x2223
+; CHECK-SD-NEXT: movk w8, #8738, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_22222222:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #572662306 // =0x22222222
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
+ %out = icmp slt i32 %in, 572662307
+ ret i1 %out
+}
+
+define i1 @sle_33333333(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_33333333:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #13108 // =0x3334
+; CHECK-SD-NEXT: movk w8, #13107, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_33333333:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #858993459 // =0x33333333
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
+ %out = icmp slt i32 %in, 858993460
+ ret i1 %out
+}
+
+define i1 @sle_44444444(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_44444444:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #17477 // =0x4445
+; CHECK-SD-NEXT: movk w8, #17476, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_44444444:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1145324612 // =0x44444444
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
+ %out = icmp slt i32 %in, 1145324613
+ ret i1 %out
+}
+
+define i1 @sle_55555555(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_55555555:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #21846 // =0x5556
+; CHECK-SD-NEXT: movk w8, #21845, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_55555555:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1431655765 // =0x55555555
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
+ %out = icmp slt i32 %in, 1431655766
+ ret i1 %out
+}
+
+define i1 @sle_66666666(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_66666666:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #26215 // =0x6667
+; CHECK-SD-NEXT: movk w8, #26214, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_66666666:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1717986918 // =0x66666666
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
+ %out = icmp slt i32 %in, 1717986919
+ ret i1 %out
+}
+
+define i1 @sle_77777777(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_77777777:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #30584 // =0x7778
+; CHECK-SD-NEXT: movk w8, #30583, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_77777777:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #2004318071 // =0x77777777
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, le
+; CHECK-GI-NEXT: ret
+ %out = icmp slt i32 %in, 2004318072
+ ret i1 %out
+}
+
+define i1 @sle_88888888(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_88888888:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #34953 // =0x8889
+; CHECK-SD-NEXT: movk w8, #34952, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_88888888:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-2004318072 // =0x88888888
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, -2004318071
+ ret i1 %out
+}
+
+define i1 @sle_99999999(i32 noundef %in) {
+; CHECK-SD-LABEL: sle_99999999:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #39322 // =0x999a
+; CHECK-SD-NEXT: movk w8, #39321, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, lo
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sle_99999999:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-1717986919 // =0x99999999
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ls
+; CHECK-GI-NEXT: ret
+ %out = icmp ult i32 %in, -1717986918
+ ret i1 %out
+}
+
+define i1 @sge_11111111(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_11111111:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #4368 // =0x1110
+; CHECK-SD-NEXT: movk w8, #4369, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_11111111:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #286331153 // =0x11111111
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
+ %out = icmp sgt i32 %in, 286331152
+ ret i1 %out
+}
+
+define i1 @sge_22222222(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_22222222:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #8737 // =0x2221
+; CHECK-SD-NEXT: movk w8, #8738, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_22222222:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #572662306 // =0x22222222
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
+ %out = icmp sgt i32 %in, 572662305
+ ret i1 %out
+}
+
+define i1 @sge_33333333(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_33333333:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #13106 // =0x3332
+; CHECK-SD-NEXT: movk w8, #13107, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_33333333:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #858993459 // =0x33333333
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
+ %out = icmp sgt i32 %in, 858993458
+ ret i1 %out
+}
+
+define i1 @sge_44444444(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_44444444:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #17475 // =0x4443
+; CHECK-SD-NEXT: movk w8, #17476, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_44444444:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1145324612 // =0x44444444
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
+ %out = icmp sgt i32 %in, 1145324611
+ ret i1 %out
+}
+
+define i1 @sge_55555555(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_55555555:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #21844 // =0x5554
+; CHECK-SD-NEXT: movk w8, #21845, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_55555555:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1431655765 // =0x55555555
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
+ %out = icmp sgt i32 %in, 1431655764
+ ret i1 %out
+}
+
+define i1 @sge_66666666(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_66666666:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #26213 // =0x6665
+; CHECK-SD-NEXT: movk w8, #26214, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_66666666:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #1717986918 // =0x66666666
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
+ %out = icmp sgt i32 %in, 1717986917
+ ret i1 %out
+}
+
+define i1 @sge_77777777(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_77777777:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #30582 // =0x7776
+; CHECK-SD-NEXT: movk w8, #30583, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, gt
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_77777777:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #2004318071 // =0x77777777
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, ge
+; CHECK-GI-NEXT: ret
+ %out = icmp sgt i32 %in, 2004318070
+ ret i1 %out
+}
+
+define i1 @sge_88888888(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_88888888:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #34951 // =0x8887
+; CHECK-SD-NEXT: movk w8, #34952, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_88888888:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-2004318072 // =0x88888888
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, -2004318073
+ ret i1 %out
+}
+
+define i1 @sge_99999999(i32 noundef %in) {
+; CHECK-SD-LABEL: sge_99999999:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #39320 // =0x9998
+; CHECK-SD-NEXT: movk w8, #39321, lsl #16
+; CHECK-SD-NEXT: cmp w0, w8
+; CHECK-SD-NEXT: cset w0, hi
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sge_99999999:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-1717986919 // =0x99999999
+; CHECK-GI-NEXT: cmp w0, w8
+; CHECK-GI-NEXT: cset w0, hs
+; CHECK-GI-NEXT: ret
+ %out = icmp ugt i32 %in, -1717986920
+ ret i1 %out
+}
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