[llvm] [SPIR-V] Validate and fix bit width of scalar registers (PR #95147)

[via llvm-commits]

github-actions[bot] wrote:

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git-clang-format --diff 2ca8c856eeae739ec1e7242ee7e69f99ecf376d3 d8e17b64ecf0dad9ba7dcd6174e0eae9ada3c1eb -- llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index aaba6e873e..53e0432192 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -422,7 +422,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
       unsigned MIOp = MI.getOpcode();
 
       // validate bit width of scalar registers
-      for (const auto& MOP : MI.operands())
+      for (const auto &MOP : MI.operands())
         if (MOP.isReg())
           widenScalarLLTNextPow2(MOP.getReg(), MRI);
 

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https://github.com/llvm/llvm-project/pull/95147