[llvm] e9a3623 - [CodeGen] Preserved additional analyses in StackSlotColoring pass. (#93779)

[via llvm-commits]

Author: Vikash Gupta
Date: 2024-06-11T12:10:40+05:30
New Revision: e9a362362e03c6aea7a64473e8b8bb9140fd3855

URL: https://github.com/llvm/llvm-project/commit/e9a362362e03c6aea7a64473e8b8bb9140fd3855
DIFF: https://github.com/llvm/llvm-project/commit/e9a362362e03c6aea7a64473e8b8bb9140fd3855.diff

LOG: [CodeGen] Preserved additional analyses in StackSlotColoring pass. (#93779)

The pass pipeline of some architecture splits register allocation phase
based on different register classes. As some analyses need to be
computed at the beginning of the register allocation and kept alive till
all values are assigned to some physical registers.

This poses challenge with objective of introducing StackSlotColoring
after partial virtual registers are assigned to physical registers, in
order to optimize stack slots usage.As this pass doesn't preserve few
analysis yet to be needed by the register allocation of the remaining
virtual registers, necessiating them to be kept preserved.

Added: 
    

Modified: 
    llvm/lib/CodeGen/StackSlotColoring.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp
index 9fdc8a338b52a..eb7a113b575f7 100644
--- a/llvm/lib/CodeGen/StackSlotColoring.cpp
+++ b/llvm/lib/CodeGen/StackSlotColoring.cpp
@@ -13,6 +13,7 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveDebugVariables.h"
 #include "llvm/CodeGen/LiveInterval.h"
 #include "llvm/CodeGen/LiveIntervalUnion.h"
 #include "llvm/CodeGen/LiveIntervals.h"
@@ -64,6 +65,7 @@ namespace {
     MachineFrameInfo *MFI = nullptr;
     const TargetInstrInfo *TII = nullptr;
     const MachineBlockFrequencyInfo *MBFI = nullptr;
+    SlotIndexes *Indexes = nullptr;
 
     // SSIntervals - Spill slot intervals.
     std::vector<LiveInterval*> SSIntervals;
@@ -152,6 +154,14 @@ namespace {
       AU.addRequired<MachineBlockFrequencyInfo>();
       AU.addPreserved<MachineBlockFrequencyInfo>();
       AU.addPreservedID(MachineDominatorsID);
+
+      // In some Target's pipeline, register allocation (RA) might be
+      // split into multiple phases based on register class. So, this pass
+      // may be invoked multiple times requiring it to save these analyses to be
+      // used by RA later.
+      AU.addPreserved<LiveIntervals>();
+      AU.addPreserved<LiveDebugVariables>();
+
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
@@ -496,8 +506,11 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {
     ++I;
   }
 
-  for (MachineInstr *MI : toErase)
+  for (MachineInstr *MI : toErase) {
+    if (Indexes)
+      Indexes->removeMachineInstrFromMaps(*MI);
     MI->eraseFromParent();
+  }
 
   return changed;
 }
@@ -515,6 +528,7 @@ bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) {
   TII = MF.getSubtarget().getInstrInfo();
   LS = &getAnalysis<LiveStacks>();
   MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
+  Indexes = &getAnalysis<SlotIndexes>();
 
   bool Changed = false;