[llvm] [AMDGPU][WIP] Optimize SGPR spills (PR #93668)

[Vikash Gupta via llvm-commits]

================
@@ -362,10 +362,12 @@
 ; GCN-O1-NEXT:        Machine Optimization Remark Emitter
 ; GCN-O1-NEXT:        Greedy Register Allocator
 ; GCN-O1-NEXT:        Virtual Register Rewriter
+; GCN-O1-NEXT:        Stack Slot Coloring
 ; GCN-O1-NEXT:        SI lower SGPR spill instructions
 ; GCN-O1-NEXT:        Virtual Register Map
 ; GCN-O1-NEXT:        Live Register Matrix
 ; GCN-O1-NEXT:        SI Pre-allocate WWM Registers
+; GCN-O1-NEXT:        Live Stack Slot Analysis
----------------
vg0204 wrote:

As there already exists a PR #93779, which deals with preserving additional analysis to be later used by RA passes, can I incorporate these changes there OR open a new follow-up PR?

https://github.com/llvm/llvm-project/pull/93668