[llvm] [SelectionDAG]: Add more cases for UDIV, SDIV, SRA, and SRL (PR #89522)

[Jay Foad via llvm-commits]

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@@ -5612,12 +5683,32 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
     return ne && *ne;
   }
 
-  case ISD::MUL:
+  case ISD::MUL: {
     if (Op->getFlags().hasNoSignedWrap() || Op->getFlags().hasNoUnsignedWrap())
       if (isKnownNeverZero(Op.getOperand(1), Depth + 1) &&
           isKnownNeverZero(Op.getOperand(0), Depth + 1))
         return true;
+
+    KnownBits XKnown = computeKnownBits(Op.getOperand(0), Depth + 1);
+    if (XKnown.One[0])
+      if (isKnownNeverZero(Op.getOperand(1), Depth + 1))
+        return true;
+
+    KnownBits YKnown = computeKnownBits(Op.getOperand(1), Depth + 1);
+    if (YKnown.One[0])
+      if (XKnown.isNonZero() || isKnownNeverZero(Op.getOperand(0), Depth + 1))
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jayfoad wrote:

Suggest removing `XKnown.isNonZero() || ` here since it will be handled by the general case below (and the general case is not slow).

https://github.com/llvm/llvm-project/pull/89522