[llvm] [AMDGPU][LIT] Added a MIR LIT showing the SGPR spills (PR #94584)

[Vikash Gupta via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -verify-machineinstrs -stress-regalloc=3 -start-before=greedy -stop-after=si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=SGPR_SPILLED %s
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vg0204 wrote:

As I was trying to generate post optimized SGPR spills by adding " --start-before=stack-slot-coloring --stop-after=si-lower-sgpr-spills", I found that if stackSlotColoring(SSC) is introduced before SILowerSGPRSpills, it really depends on regAlloc. As StackSlotColoring pass uses LiveStack(LS) analysis results {which is currently computed at RegAlloc phase, as LS itself do not do anything}. So if we invoke SSC directly on 'input.mir' without LS results available, we acutually won't see any stack slots optimization (in turn no sgpr spill optimization).    

https://github.com/llvm/llvm-project/pull/94584