[llvm] 84b3fe6 - [RISCV] Flatten VPatBinaryW_VI_VWSLL and VPatBinaryW_VX_VWSLL into VPatBinaryW_VV_VX_VI_VWSLL. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 7 18:53:54 PDT 2024
Author: Craig Topper
Date: 2024-06-07T18:48:20-07:00
New Revision: 84b3fe65f9a739cc22d031dd50e2552e2db3f479
URL: https://github.com/llvm/llvm-project/commit/84b3fe65f9a739cc22d031dd50e2552e2db3f479
DIFF: https://github.com/llvm/llvm-project/commit/84b3fe65f9a739cc22d031dd50e2552e2db3f479.diff
LOG: [RISCV] Flatten VPatBinaryW_VI_VWSLL and VPatBinaryW_VX_VWSLL into VPatBinaryW_VV_VX_VI_VWSLL. NFC
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 82b3b6165e968..98b5aeef9fe2d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -1031,39 +1031,27 @@ multiclass VPatBinaryV_VV_VX_VI_VROR<string intrinsic, string instruction,
VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
-multiclass VPatBinaryW_VI_VWSLL<string intrinsic, string instruction,
- list<VTypeInfoToWide> vtilist> {
- foreach VtiToWti = vtilist in {
- defvar Vti = VtiToWti.Vti;
- defvar Wti = VtiToWti.Wti;
- defm : VPatBinary<intrinsic, instruction # "_VI_" # Vti.LMul.MX,
- Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
- Vti.Log2SEW, Wti.RegClass,
- Vti.RegClass, uimm5>;
- }
-}
-
-multiclass VPatBinaryW_VX_VWSLL<string intrinsic, string instruction,
- list<VTypeInfoToWide> vtilist> {
+multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
+ list<VTypeInfoToWide> vtilist>
+ : VPatBinaryW_VV<intrinsic, instruction, vtilist> {
foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti;
defvar kind = "V"#Vti.ScalarSuffix;
let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,
- GetVTypePredicates<Wti>.Predicates) in
- defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
- Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
- Vti.Log2SEW, Wti.RegClass,
- Vti.RegClass, Vti.ScalarRegClass>;
+ GetVTypePredicates<Wti>.Predicates) in {
+ defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
+ Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
+ Vti.Log2SEW, Wti.RegClass,
+ Vti.RegClass, Vti.ScalarRegClass>;
+ defm : VPatBinary<intrinsic, instruction # "_VI_" # Vti.LMul.MX,
+ Wti.Vector, Vti.Vector, XLenVT, Vti.Mask,
+ Vti.Log2SEW, Wti.RegClass,
+ Vti.RegClass, uimm5>;
+ }
}
}
-multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
- list<VTypeInfoToWide> vtilist>
- : VPatBinaryW_VV<intrinsic, instruction, vtilist>,
- VPatBinaryW_VX_VWSLL<intrinsic, instruction, vtilist>,
- VPatBinaryW_VI_VWSLL<intrinsic, instruction, vtilist>;
-
let Predicates = [HasStdExtZvbb] in {
defm : VPatUnaryV_V<"int_riscv_vbrev", "PseudoVBREV", AllIntegerVectors>;
defm : VPatUnaryV_V<"int_riscv_vclz", "PseudoVCLZ", AllIntegerVectors>;
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