[llvm] 5422b5f - [RISCV] Rename VPseudoVWALU_VV_VX_VI to VPseudoVWSLL. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-06-07T18:42:27-07:00
New Revision: 5422b5f0287d6f0920abf1b868985575885b4d5b

URL: https://github.com/llvm/llvm-project/commit/5422b5f0287d6f0920abf1b868985575885b4d5b
DIFF: https://github.com/llvm/llvm-project/commit/5422b5f0287d6f0920abf1b868985575885b4d5b.diff

LOG: [RISCV] Rename VPseudoVWALU_VV_VX_VI to VPseudoVWSLL. NFC

The scheduler class name is hardcoded in the class so its not a
general class.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index d091077f729b8..957d295d5eca0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -452,16 +452,16 @@ multiclass VPseudoVCPOP {
   }
 }
 
-multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> {
+multiclass VPseudoVWSLL {
   foreach m = MxListW in {
     defvar mx = m.MX;
     defm "" : VPseudoBinaryW_VV<m>,
               SchedBinary<"WriteVWSLLV", "ReadVWSLLV", "ReadVWSLLV", mx,
                           forceMergeOpRead=true>;
-    defm "" : VPseudoBinaryW_VX<m>, 
+    defm "" : VPseudoBinaryW_VX<m>,
               SchedBinary<"WriteVWSLLX", "ReadVWSLLV", "ReadVWSLLX", mx,
                           forceMergeOpRead=true>;
-    defm "" : VPseudoBinaryW_VI<ImmType, m>,
+    defm "" : VPseudoBinaryW_VI<uimm5, m>,
               SchedUnary<"WriteVWSLLI", "ReadVWSLLV", mx,
                          forceMergeOpRead=true>;
   }
@@ -525,7 +525,7 @@ let Predicates = [HasStdExtZvbb] in {
   defm PseudoVCLZ   : VPseudoVCLZ;
   defm PseudoVCTZ   : VPseudoVCTZ;
   defm PseudoVCPOP  : VPseudoVCPOP;
-  defm PseudoVWSLL : VPseudoVWALU_VV_VX_VI<uimm5>;
+  defm PseudoVWSLL : VPseudoVWSLL;
 } // Predicates = [HasStdExtZvbb]
 
 let Predicates = [HasStdExtZvbc] in {